Pcb layer stackup design high speed board design

PCB Layer Stackup Design for Planes and Signal Layers

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One of the questions I often receive from designers relates to their layer stackup. New designers often think they only need 2 layers for every board they’ll design and they don’t understand when they need multiple layers. At the other extreme is the designer that thinks they need dozens of layers for simple boards.

With proper floorplanning and some size estimation, you’ll find that the answer often lies somewhere in between. In reality, the correct number of layers for a new board depends on a number of factors. The number of dedicated signal, power, and ground layers you use forms your PCB layer stackup design and depends primarily on the number of signal nets and signal bandwidths. With more signal nets comes more required signal layers, as well as reference layers for isolation. Once you look at the HDI and mixed signal regimes, PCB layer stackup design becomes something of an art form, and the exact number of layers can be difficult to predict. We’ve done controlled impedance HDI boards with ~1000 nets on as few as 8 layers (that’s 8 layers in total, not 8 signal layers plus power and ground layers), and we’ve done RF boards that require at minimum 4 layers due to the different frequencies and isolation requirements involved in the board. Let’s take a closer look at PCB layer stackup design for your next system so that you can properly plan for design and manufacturing.

Start by Counting Ground Planes

Instead of starting with the number of signal layers, I think it’s better to determine which sets of signal layers will need adjacent ground reference layers. There are a few important reasons for this:

  1. It’s required for controlled impedance. Modern digital systems use generic high speed logic families, differential signalling standards, or that interface with computer peripherals (e.g., USB, DDR, PCIe, Ethernet, etc.) will need to use controlled impedance routing. Placing the ground plane near signal traces defines the impedance of your traces and the propagation delay for signals.

  2. It helps plan return paths. In dense high speed/high frequency systems, you need to plan the return path for signals. The goal is to ensure small loop inductance for every trace in your board, and to ensure your signals do not receive excessive crosstalk or experience excessive ringing during transient switching.

  3. It helps suppress EMI. The previous point is related to reception of radiated EMI; a circuit with small loop inductance will receive low EMI from an external source or from within the board. Crosstalk and external EMI can both be suppressed by placing a ground plane near sensitive signals.

  4. It aids isolation in mixed-signal boards. Analog and digital board sections need to be isolated from each other. Placing analog and digital traces on different layers separated by a ground plane suppresses digital signal noise from interfering with analog signals.

Your typical high speed layer stackup might look something like the image shown below. In this stackup, signal layers are separated from each other with plane layers in order to provide isolation, and different types of signals are placed into different signal layers. This is one of the central aspects of PCB layer stackup design as you need to ensure different types of signals do not interfere with each other.

 

Pcb layer stackup design high speed board design

High layer count stackup for high speed/high frequency designs. The symmetric structure with alternating power/ground planes ensures sufficient isolation between different board sections.

 

There is an outdated design recommendation that should not be followed in high speed digital boards, which I’ve written about on Altium’s PCB Design Blog. This is the use of orthogonal routing on adjacent signal layers. In general, it is better to consolidate things onto the same layer and use ground planes between layers to provide isolation. This is especially true considering today’s high speed digital boards, where low-level signal bandwidths are high enough (~20 GHz) to cause capacitive coupling between adjacent signal lines. It’s better to simply separate these lines with ground planes, rather than risk unintended coupling between signal lines.

Number of Layers in PCB Layer Stackup Design

Unfortunately, there is no hard-and-fast rule on the number of signal layers you’ll need. For modern PCBs, you’ll need at least 4 (signal-power-ground-signal), and it only goes up from there, depending on the number of components, nets, and types of signals. For HDI boards, we have a situation where the number of signal nets is so high that thin layers are required to ensure impedance control during routing. For HDI boards, I tend to estimate the number of required layers will be approximately 5000*(trace width/board width). Note that this is just a rough estimate after having completed multiple projects with high net count (~500 to ~1000). For a 10 cm wide board and 10 mil traces (0.25 mm wide), this would give ~12 layers in total. We’ve done this type of board with ~1000 nets using 10 layers multiple times, so this simple formula is a decent estimate.

For other high speed boards that aren’t in the HDI regime, the number of signal layers can also depend on component size rather than primarily on net count. Physically larger components reduce available space for routing on the surface layer, and the traces will be physically larger. This often forces routing on an additional layer. Designers often have to resort to experience in order to determine the best layer count.

Power Integrity and PCB Layer Stackup Design

I've discussed power integrity and it’s relationship to PCB layer stackup design multiple times in detail on this blog, so I’ll only briefly summarize the important points. If you want to reduce jitter and voltage ripple on the PDN, then you need to have a ground plane adjacent to the power plane. This should be done for each section of the board (analog and digital) .

To learn more about PDN impedance and how it is related to your PCB layer stackup design, you can read more from some other articles on the NWES blog:

Pcb layer stackup design power gridding

Separation between AC and DC power sections with an AC input. This type of sectioning is amenable on a 4-layer board with a power plane below the surface layer. The alternative on a high layer count board is to place a dedicated set of analog power/ground planes.

An uncommon situation with power integrity and isolation is to use an analog power section that then feeds into a downstream digital section. This requires gridding out the power section and the corresponding ground section to ensure return paths do not cross, just as you normally would with high speed signals. The goal is to prevent lower frequency switching noise from any switching regulator in the digital section from coupling back into the analog power section. This is one reason that an analog power plane is often used, and this is a viable option when you have separated AC and DC power sources. For an AC-only power source that must provide power to a DC digital section and a set of analog components, you’ll have no choice but to use a separation strategy to prevent interference between power sections.

 

At NWES, we’ve designed everything from simple 2-layer boards to complex HDI PCBs for digital and analog systems. We know PCB layer stackup design and how to ensure your board operates as you intend. We're here to help electronics companies design modern PCBs and create cutting-edge technology. We've also partnered directly with EDA companies and advanced PCB manufacturers, and we'll make sure your next layout is fully manufacturable at scale. Contact NWES for a consultation.

 


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