Power integrity is one of those aspects of PCB design and analysis that is sometimes less understood than signal integrity by most designers. The two fields are definitely related. In short power integrity requires determining the voltage and current needed by components in your board, and creating the appropriate layout to deliver that power, known as a power delivery network (PDN).
Any PDN design should provide stable voltage and current, meaning that the operation of one component in your PCB does not change the power received by another component on the same power rail. While this may sound esoteric to most designers, electrical engineers that work for utilities in developing countries are likely already aware of larger-scale power integrity issues that arise when too many people plug into the electric grid. The same analogy holds for your power delivery network.
In this post, I’ll take you briefly through the central ideas involved in PDN design and the important points to analyze in your power delivery network. Any PDN simulation can be complex, especially if performed from your schematic, although there are some simple simulations you can use to examine power integrity in your PCB design. Let’s take a look at how parasitics and components in your PDN affect its operation and what you need to take into account during PDN design.
Your PDN will only be resistive when run at DC voltages. The natural DC resistance of copper in your PDN will cause some voltage drop as current moves from the power supply to components. When driven with an AC signal or a digital signal, the PDN will provide some impedance due to parasitics in your PCB, and any voltage/current on the PDN will be some function of frequency. The frequency dependence of a real PDN is responsible for many power integrity problems observed in real PCBs. It also influences how noise on your power regulator propagates through the PDN. Even if a PDN is run at DC, a DC regulator has some ripple or switching noise in the case of switching regulators. Whether you are looking at the ripple produced by noise sources or the ripple due to transients on the power bus, any ripple/ringing voltage will depend on the impedance of the PDN, which varies with frequency.
As a PCB designer, your goal in PDN design is to ensure that the PDN impedance is as flat as possible throughout the relevant frequency band you’ll be working with in your circuits. When we say that the impedance frequency is flat, we mean that the impedance does not change over some range of frequencies. To get an idea of what this means for your PCBs, let’s take a look at the example impedance spectrum for a PDN design shown in Fig. 1.
Fig. 1: Example impedance spectrum of a typical PDN without decoupling networks.
In this graph, you can see that the impedance of the PDN appears capacitive at low frequencies. There are a number of resonance (high impedance) and anti-resonance (low impedance) peaks in the spectrum. Note that this behavior is typical for a PDN that does not include decoupling network. At certain frequencies, the PDN exhibits very high or very low impedance. The impedance of this particular PDN is only flat from approximately 20 kHz to 700 kHz. The impedance determines the relationship between any ripple voltage on the power bus and any transient current that propagates in the circuit as an IC switches. If you like, you can write the ripple/ringing voltage as a function of the PDN impedance and transient current from Ohm’s law:
Eq. (1): Relationship between power rail ripple or ringing on a PDN, the transient current, and the PDN impedance as a function of frequency.
Eq. (1) is used to define a target impedance a designer should try to reach. This is defined in terms of the maximum allowed voltage ripple as a percentage of the desired supply voltage and the maximum transient current:
Eq. (2): Target impedance formula for a desired supply voltage on a PDN and the maximum allowed transient current.
With Eq. (2), we can now determine the target PDN impedance we need to suppress voltage fluctuations on a power bus for digital and analog ICs. In most cases, you cannot get the PDN impedance spectrum to be completely flat over the required frequency range, but you can get it to be less than your target value defined in Eq. (2). The idea is to design the PDN spectrum so that the power rail ripple is within a desired bandwidth is minimized. Let’s look at each type of signal and transient oscillation suppression method in more depth:
When a digital IC switches, the voltage regulator on the PDN needs to supply some extra current (up to its maximum output) so that the downstream IC can supply the desired output signal. This switching action creates a transient oscillation on the power rails, which can be seen as a voltage ripple in the PDN. If a large number of ICs switch simultaneously, this causes the voltage seen by all other ICs on a power bus to change significantly. If the current drawn from the supply is large and the PDN impedance is large at the transient oscillation frequency, this can cause unintentional switching in digital ICs, which significantly increases BER.
If you look at Eqs. (1) and (2), we see that if the voltage ripple will be large if the PDN impedance is large at the current’s transient oscillation frequency. The allowed ripple in Eq. (2) should be chosen so that the voltage seen by a downstream component is less than its noise margin. If your components are slightly overdriven, you can tolerate a slightly larger voltage ripple, but your components will have higher junction temperature. This exacerbates thermal management problems for components that run at high frequency and have high pin count (e.g., FPGAs).
Digital signals are actually composed of a summation of an infinite number of Fourier harmonics. ~75% of the power density is contained between below the signal’s knee frequency, which is approximately 0.35 divided by the signal rise time. If you want to reduce the amplitude of any transient oscillation on its power bus, then you should try to set the PDN resonance with the smallest frequency to be larger than the signal’s knee frequency.
You should try to reach the conditions shown in Fig. 2:
Fig. 2: Zoomed-in view of the impedance spectrum in Fig. 1. A Fourier spectrum for a square wave is shown as an example. Here we see that there is a single PDN resonance between the clock frequency and the knee frequency, but the impedance at the peak (~1.5 GHz) is less than the target impedance.
Changing the resonance frequency of the PDN to be much larger than the signal’s knee frequency (which is generally larger than the underdamped transient oscillation frequency) will only reduce the amplitude of the ripple voltage, as shown in Eq. (1). This will not completely suppress any underdamped transient oscillation. To do this, you need to increase the damping in the power bus. We’ll talk about this in terms of your schematic, layout, stackup, and simulations in more depth below.
If your power bus also provides power to analog ICs, any transient oscillation or noise on the power bus will be copied onto the output of your analog ICs. This is one reason why some designers will place a large inductor or ferrite before the power pin on DAC/ADC ICs. This effectively forms a low pass filter, which allows the desired DC signal to reach the IC while filtering out the transient oscillation before it reaches the power pin. Be careful with any components used for decoupling as parasitics cause these components to behave as RLC circuits.
Note that even if the impedance band is flat between the clock and knee frequencies, the transient response can still appear as an underdamped oscillation. It is best that you also use one or more decoupling capacitors on your PDN to change the damping level for any transient oscillation in the PDN. The goal is to bring the transient response into the overdamped regime. Take a look at our simulation guide to learn more about these techniques.
The best way to do this is to determine the appropriate decoupling capacitance that will compensate for the transient response and transition the response to critical damping. Learn more about sizing decoupling capacitors and working with decoupling inductors in my recent articles on Altium’s PCB design blog. Note that, when you include a decoupling capacitor in your schematic, you should account for the capacitors’ self-resonance frequency.
Even if you size your capacitor to provide the required charge to compensate the transient current, you may still see some ringing on the power rails as you are still not in the critically damped or overdamped regime. In this case, you can simply use a larger capacitor. Normally, it is better to use multiple decoupling capacitors in parallel on the PDN rather than a single larger capacitor as this ensures the self-resonance frequency of this decoupling capacitor group will be larger than that for a single capacitor.
The other way to do this is to properly size your power and ground planes with the appropriate spacing. This is why boards with extremely fast digital ICs use power and ground planes on adjacent layers as this provides very high capacitance. This contributes to the total capacitance seen by a transient oscillation on the power bus. When combined with decoupling capacitors, you can overdamp the transient response. Fig. 3 shows a simplified schematic model you can use for PDN design.
Fig. 3: A simple PDN design in a schematic.
You can determine the PDN impedance spectrum using a frequency sweep in your schematic, and you can examine the transient response in the time domain with a transient simulation. You can apply these simulations directly to your schematic as long as you account for parasitics in your PCB layout. You should examine the IR drop throughout your PDN using a PDN analyzer simulation. This will tell you how much voltage is dropped due to DC resistance in your power and ground planes. This can also help you identify potential hot spots in your board. You can do this directly from your layout.
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