If you read a lot of guides on high speed PCB design, you’ll see many mentions to impedance matching. This important process is designed to ensure signals transmit between driver and receiver components without signal reflections and with the required power transmission into the receiving component.

The process for impedance matching in high speed PCB designs depends on the signalling standard, supply voltage levels, and signal levels. We often say that PCB traces should simply have 50 Ohm impedance, but this becomes more complicated when dealing with coupling between differential pairs. High speed digital designers should take time to understand this important process and design interconnects with proper termination to match their signalling standard.

Because impedance mismatches between components, traces, and vias depend on trace geometry, logic family, and coupling, you need to carefully design traces to have the proper single-ended and differential impedance. Different logic families have signalling standards that define how a driver, trace, and receiver need to be terminated to provide consistent impedance matching in PCB interconnects. While we’ll look specifically at PCB transmission lines between integrated circuits, the same ideas apply to interconnects inside an integrated circuit, where transmission lines need to be carefully designed to ensure impedance matching.

For single-ended signals, you simply need to worry about the input impedance (for receivers) and output impedance (for drivers). Note that dispersion in the PCB substrate can complicate impedance matching, and your goal should be to adjust the geometry to ensure impedance matching throughout the signal bandwidth. This can become a complex optimization problem, which I’ve discussed elsewhere on this blog and in a few articles on Altium’s PCB Design Blog.

IC manufacturers have gotten much better about reporting the input and output impedance spectra for their components. At minimum, they should tell you the pin-package lead inductance, input capacitance, and equivalent input resistance. All these values depend on logic family. You can then use any of the standard impedance matching schemes for high speed interconnects to prevent signal reflection and ensure power transfer. The standard methods used for impedance matching in single-ended signalling standards are shown below. Note that each of these has a fly-by variation, where the termination resistor is connected directly to the component pad rather than the trace.

*Impedance matching schemes for single-ended transmission lines.*

There are many high speed interfaces that use differential signaling. Some of these (e.g., LVDS) have high input impedance, while others have fixed input impedance. Note that some integrated circuits may have on-chip termination (e.g., high pin count LVDS devices). These high speed differential signalling standards include the following:

**LVDS (Low-Voltage Differential Signaling):**High input impedance, uses a parallel resistor at the receiver to match the receiver’s input impedance to the 100 Ohms differential impedance of the differential pair.**CML (Current Mode Logic):**Specified input and output impedance of 50 Ohms, which is referenced to the single-ended impedance of each trace in a differential pair. CML chips may not have input termination resistors and require pull-up and pull-down resistors to match the input level to the Vdd level on the chip (see the application notes linked below).**PECL (Pseudo-Emitter Coupled Logic):**Traces have 100 ohm differential impedance and 50 Ohms single-ended impedance. Outputs have low impedance (~5 Ohms), which requires pull-up/pull-down resistors for impedance matching.**HSTL (High Speed Transceiver Logic):**There are four classes of HSTL for signalling between CMOS and BiCMOS devices, each requiring different termination methods.**PCIe:**Traces on the bus must have differential impedance of 92 Ohms (COMCDG Rev. 1.0) or 85 Ohms (COMCDG Rev. 2.0 and 3.0).**Ethernet:**Ethernet lines are differential pairs with 100 Ohms differential impedance with single-ended impedance of 50 Ohms.**USB:**50 Ohms characteristic impedance, differential impedance matching at 90 Ohms, which matches the differential impedance of a USB cable.

There are other high speed interfaces used in computer peripherals that are related to those shown above; LVPECL (low-voltage PECL) is one example. If you need to connect between different high speed differential signalling standards (e.g., LVDS driver to a PECL receiver), there is a certain network of pull-up and pull-down resistors you can use to ensure impedance matching. Take a look at this application note from Maxim Integrated and this application note from Renesas to see how this is done for the common high-speed interfaces.

If you look through the above list, you’ll see that the specifications state that an individual trace must have 50 Ohms single-ended impedance and 100 Ohms differential impedance. Due to coupling between each trace in a differential pair, two 50 Ohms traces that are driven differentially will not have differential impedance of 100 Ohms. By definition, two single-ended traces, each with characteristic impedance Z0, cannot have differential impedance of 2Z0; the real differential impedance will be less than 2Z0. How then can a real differential pair be constructed with impedance matching to 50 Ohms (single-ended) AND to 100 Ohms (differential).

In theory, there are two ways to accommodate this:

- Design each trace with slightly larger than 50 Ohms, and design the pair so that the differential impedance is slightly under 100 Ohms. As long as both values are within tolerances, then you are fine.
- Simply over-design each single-ended trace above 50 Ohms and place a series resistor at the driver end, and then set the differential impedance to 100 Ohms.

In LVDS, we only really care about the differential impedance seen at the receiver. The image below shows the termination scheme used with two 50 Ohms traces in a differential pair; the end is intentionally terminated at 100 Ohms with a parallel resistor.

*LVDS impedance matching scheme with a parallel resistor at the desired differential impedance.*

The example above is instructive: it should show that the value we really care about is the differential impedance as this is the value determining how the signal is read at the receiver. For more help with board layout, take a look at our high speed PCB design guidelines, which apply to single-ended and differential pairs in your board.

**The design team at NWES specializes in high speed and high frequency board design. We know how to design your board with consistent impedance matching, how to ensure signal integrity, and how to maintain power integrity. We’re here to help electronics companies design modern PCB and create cutting-edge technology. We’re also a digital marketing firm, and we provide SEO-driven content marketing services for the products we design. We’re the best choice to market your product because we’ve built it and we’ve used it. Contact NWES for a consultation.**