Power integrity in PCB design is all about ensuring the power you input into your board reaches your downstream components. Here, we’re not so worried about power regulator design, although this is an important topic. Once power is output from your regulator, what happens once it travels across your power distribution network (PDN)?
If power is lost on the way from your regulator output to the downstream components, your components may not receive the power they need to operate properly. There are some simple solutions you can use to prevent power drop. In Part 1 of this series on power integrity in PCB design, I’ll show you the process needed to ensure components in your board receive all the power you output from your power regulator. Once power is put into the PDN and reaches your components, you’ll need to ensure this output power remains stable as your device operates; I’ll discuss this in an upcoming article.
Every electronics student unknowingly performs DC analysis in their Electronics 101 classes when they analyze circuit diagrams with a DC power source. Circuit diagrams are simple tools for understanding electrical behavior, but they miss important points of real systems, which can only be examined by looking at your PCB layout. In a real PCB, ensuring DC power integrity centers around making sure DC power is not lost between the power regulator and your components. Although this involves some complicated looking graphs and simulation tools, examining DC power integrity is surprisingly simple and only requires using Ohm’s law.
Why would DC power be lost between the regulator output and your components? Very simply, this occurs due to the finite electrical conductivity of all materials. Your PDN is made up of power planes, ground planes, vias, and possibly some surface traces or rails. Each of these elements has some DC resistance, and this resistance causes some power to be dissipated as heat as your board operates. To determine the power drop per unit area at any point in the PDN, simply multiply the squared current at any point along the PDN by the sheet resistance at that point:
Power loss per unit area at any point in the PDN.
The sheet resistance can be calculated from the DC conductivity of the metal that makes up the PDN. The voltage dropped between two points in the PDN is equal to the current between two points multiplied by the resistance between the two points. This is simply Ohm’s law. Just as sheet resistance can be calculated using electrical conductivity, so can total resistance between two points. Copper conductivity values reported in industry literature are approximately 47 MS/m at room temperature, which are similar to the values for electro-deposited copper.
Because the PDN in a PCB is a very complicated structure, calculating all this by hand is an intractable problem. This is why simulation tools are now the industry standard for analyzing DC power integrity in PCB design. These tools allow you to visualize voltage drop in your PDN as a heat map. High quality PCB design tools will include this type of simulator for DC analysis.
To analyze power integrity in PCB design with DC analysis, it helps to know what goes into a DC power integrity simulation. Here are some of the key points to understand:
The image below shows an example DC analysis result for a PCB. In this heat map, the voltage and current can be visualized using a color scale. Most simulators will show the entire color scale, but be careful to look at the values on the color scale, especially when examining the voltage distribution. The color on the scale might change wildly, even though the voltage drop may be extremely low. The same type of visualization is seen in results for current density.
Heat map showing DC voltage distribution across a power plane in a PCB.
The values you see in a heat map for the voltage distribution are referenced with respect to your ground potential (i.e., 0 V at the power supply return point). The voltage drop between two points is just the differences in voltages at each point. For the current distribution, what you are seeing is not an AC return path, i.e., it is not the path of least impedance. However, some tools will allow you to place contour lines that show the path of least resistance for current. The points where current density is largest AND a plane is narrow are also the regions where the voltage drop will be largest; these regions will have relatively high current and resistance, so the voltage drop across these areas will be large.
The amount of DC power lost as heat is proportional to the current at any point squared (see the above equation). In other words, a small change in current causes a large change in DC power loss. If the total current or current density through a region is larger, more power is lost to heat in the device. Alternative materials can help bring down temperature rise somewhat, but the primary method of reducing current density, and thereby reducing power loss and voltage drop, is to change the size of the ground plane and the copper weight in the ground plane.
From looking at the previous two points, one can see that the way to prevent DC voltage drop is to simply adjust the size of the power and ground planes. When the PDN resistance is large, the losses will be larger for a given current density. If you want to minimize losses in your PDN, you need to use heavier copper for power and ground planes. You should also opt to make the planes wider; don’t create regions in your PDN that are narrow. This is one reason designers often place a uniform copper plane throughout the ground layer with heavy copper (at least 1 oz./sq. ft.); this plane will have minimized DC resistance and losses. When the current density is lower, it’s appropriate to use power rails on the surface layer, rather than a continuous ground plane, but only if the board is not running at very high speed (<1 ns rise time) or high frequencies (100’s of MHz or higher). An example showing large losses across power rails in a PDN is shown below.
DC voltage drop across power rails in a PCB.
At the extreme, if a portion of the ground plane has high resistance, temperature rise can be large enough to cause delamination on the surface, leading to board failure. The IP-2152 standard should be used to design copper traces and plane layers to accommodate high current density. Designers often use this specification with conservative assumptions to accommodate a higher temperature increase than intended.
Note that AC analysis is more complex and requires looking at the PDN impedance, rather than just PDN resistance. Designing your PDN impedance is all about ensuring stability when a circuit block is operating, rather than just looking at DC losses. You still want your PDN to have low DC losses, but the resistance and reactance (or impedance, collectively) of your PDN will determine how transient currents on the PDN lead to voltage spikes and dips at the supply/ground pins of your components. To learn more about the interaction between high frequency/high speed digital signals and your PDN, read some of our other articles:
At NWES, we take care to examine every aspect of your board, including power integrity in PCB design. We know how to create a high quality, fully manufacturable PCB layout for your system. We're here to help electronics companies design modern PCBs and create cutting-edge technology. We've also partnered directly with EDA companies and advanced PCB manufacturers, and we'll make sure your next layout is fully manufacturable at scale. Contact NWES for a consultation.