Power integrity is more than a simple buzz word, it is critical in low voltage systems that use digital ICs with high gate count, as well as in analog systems that are operating at higher frequencies. Decoupling is an important aspect of power integrity, and the typical method for providing stable power to digital ICs like FPGAs and MCUs is to use one or more decoupling capacitors.
Using a decoupling capacitor in isolation, i.e., without closely spaced power and ground layers, was fine in the past, particularly in systems with slower rise times and at lower frequencies. Devices with microwave/mmWave analog signals, and digital systems with knee frequencies reaching mmWave levels, require much greater decoupling compared to slower systems. Before we get into choosing the right decoupling capacitor size for your system, it helps to know the exact function of a decoupling capacitor. As we’ll see, a decoupling capacitor doesn’t “decouple” anything; it’s job is to act as a large charge reservoir. Keeping this point in mind will help you determine the right decoupling capacitor size.
Power supplies are not perfect systems. Switching regulators are designed to provide stable power output without residual ripple from AC-DC or DC-DC conversion. Any noise that is output from your power supply can cause major performance degradation in downstream ICs. Some examples include reduced noise margin and increased jitter. In addition, when a downstream IC with high gate count switches, a transient response will appear on the power bus. This appears as a current spike and typically underdamped oscillation (ringing) on the power rail that can cause the voltage seen by the IC to decrease. This also causes a large opposing current to flow through ground, leading to a voltage drop at the output, known as ground bounce.
This ringing on a power bus is unavoidable as it occurs when a downstream IC switches and draws a large amount of current from the power supply. The power supply cannot act instantly to provide the charge required by the IC. This means the designer needs to incorporate some other way to provide the charge and current required by the IC in order to ensure the power bus voltage remains stable.
One of the most common ways to reduce noise on the power rail is to place a capacitor very close to the IC. This capacitor is called a decoupling capacitor; it’s job is to act as a charge reservoir, and the capacitor will discharge when the IC switches, providing some current to the downstream IC. In other words, a decoupling capacitor is meant to cancel out any transient current fluctuations on your power bus and any residual switching noise from the power supply so that these fluctuations do not affect the voltage seen by the downstream IC. Note that a decoupling capacitor is not a special type of capacitor; this term refers to the function of a capacitor rather than its construction. Technically, any capacitor can be used for decoupling if it is sized properly.
The decoupling capacitor size you need can be calculated by considering the impedance of your PDN and the charge required by the downstream IC. Analog systems function differently than digital systems, and the primary concern for choosing a decoupling capacitor size is to consider the capacitors effect on the PDN. Let’s look at choosing a decoupling capacitor for a digital PDN first, then we’ll look at analog systems.
Determining the required decoupling capacitor size and placement is key to suppressing ripple and other noise sources on your PDN. In the forthcoming discussion, the formula below is only valid when your signal bandwidth (0.35 divided by the rise time) is less than the self-resonance frequency of the decoupling capacitor. The easiest way to size a decoupling capacitor is to determine the charge required by a switching digital IC on the power rail. This can be easily calculated by taking the maximum possible current required by the IC and multiplying this by the signal rise time. When taken with the required IC voltage:
Eq. (1): Decoupling capacitor size based on the current draw during switching and desired IC voltage.
In terms of the PDN, you can size can also determine the decoupling capacitor size based on the slope at the first PDN resonance and the desired PDN impedance. The PDN resonance structure has to be measured using a vector network analyzer or simulated using frequency sweeps in post-layout simulations. However, if you know your PDN resonance structure, you can use the desired PDN impedance value (see this article for the required equation) to calculate the total decoupling capacitance as shown in the image below.
You can determine the required decoupling capacitor size using the slope of the PDN impedance at lowest order resonance. Thanks to Keysight for this graphic.
When there is some conflict between these values, it is best to opt for the larger of the two values as you want to provide sufficient charge to support switching.
Voltage regulators are intended to swap residual ripple from AC-DC or DC-DC conversion for PWM switching noise. This noise can be filtered, but it will still degrade the output from analog ICs. When considering providing stable power for an analog IC, the decoupling capacitor will be constantly charging and discharging as the IC operates. One simple equation for sizing the decoupling capacitor is shown below:
Eq. (2): A simple equation for decoupling capacitor size for analog ICs.
In Eq. (2), the current draw by the IC tends to be a monotonically increasing function of the IC voltage and frequency, so increasing both quantities does not necessarily mean that a smaller capacitor is required.
The best (and most difficult) way to determine the best decoupling capacitor size is to use the target PDN impedance spectrum. Note that the spectrum will depend on the value of the decoupling capacitance and frequency, so there is no simple closed-form equation that you can use to calculate the decoupling capacitor size. Instead, you have the following transcendental equation:
Eq. (3): Decoupling capacitor size based on required voltage ripple, target PDN impedance, and target PDN voltage.
In this equation, one can see that a lower target PDN impedance requires a larger decoupling capacitor size. Note that the target PDN impedance and the PDN voltage ripple will both be functions of capacitance, making this a very complicated problem to solve analytically. Solving this particular problem requires an iterative numerical solution for determining the value of C, ideally with a post-layout simulation. To my knowledge, there are no commercial solvers that address this problem. Regardless, the decoupling capacitor should be oversized to provide sufficient charge to support an operating IC.
Eq. (3) is also more accurate in that it can incorporate the effects of the decoupling capacitor’s self-resonance frequency and any resonances that arise due to parasitics in your layout. Parasitics are quite important, especially parasitic inductance. In particular, reducing loop inductance in the circuit block with the decoupling capacitor requires placing the decoupling capacitor close to the relevant IC. In addition, with low-level ICs, you should always use adjacent power and ground planes to provide sufficient interplanar capacitance in your board. This will minimize voltage ripple on the PDN as an IC operates.
Regarding self-resonance, you should select decoupling capacitors with sufficiently high self-resonance frequencies based on your signal bandwidth or operating frequency. When you get into the GHz range, you should look to microwave component manufacturers for capacitors with high self-resonance frequencies. Commercially available RF-specific capacitors have self-resonance frequencies reaching into the GHz range, making them ideal for ultra-fast digital systems and ultra-high frequencies. This is quite important the impedance provided by a capacitor will appear inductive beyond the self-resonance frequency, which causes the PDN impedance to be higher, thus increasing ripple voltage.
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