Schematic vs layout for an FPGA board

Schematic vs. Layout: PCB Geometry, Parasitics, and Signal Integrity

By ZM Peterson • Oct 2, 2019

Any designer that has not dived into the deep world of PCB design and may not be aware of the important differences between a schematic diagram and a PCB layout. To quote the great Eric Bogatin, the distinction between a schematic diagram and a PCB layout lives in the white space of your schematic.

In other words, the schematic does not account for how electronic components are arranged on the board, nor does it account for the traces between components. It also does not account for the arrangement of ground and power planes in a real circuit board. All of these aspects are important determinants of signal integrity in a real PCB.

When you start to understand some of the basic physics that govern electromagnetism, it should become obvious why a schematic diagram does not accurately represent the behavior of real circuits on a PCB. As a result, simulations that you perform with your circuit schematic will are unlikely to represent the real behavior you would see in a real PCB.

Simulation results from your schematic may not indicate any signal integrity problems, but a poor layout will cause problems like crosstalk, unwanted resonances, ringing, and other problems. With these facts in mind, let's take a look at the reasons for these differences and how you can overcome some simple problems in your PCB layout to ensure signal integrity.

PCB Schematic vs. Layout: What's the Difference?

In short, every difference between the behavior you determine from simulations with your schematic and your PCB layout are due to the geometry of real circuits on your PCB. Every PCB design starts with circuit diagrams that are eventually built into a schematic diagram. This important document represents the foundation of your circuit board and gives you a reference for your PCB layout. Your schematic diagram will show each circuit and its components in a typical 2D CAD assembly drawing.


Schematic vs layout for a DDR3 memory stick

Fig. 1. PCB schematic vs. layout for an example DDR3 memory stick project from Altium Designer.


Once you've finished schematic capture, you're ready to translate each circuit and the connections between components into a realistic PCB layout using a schematic import tool. This creates an initial layout and allows you to arrange your components as you deem fit. Your PCB layout reflects the real way in which your circuits behave, and it determines the distribution of the electromagnetic field throughout your system. Your PCB layout carries shows the arrangement of traces, planes in each layer, components, and other conductive elements that are responsible for many signal and power integrity problems that cannot be determined from a schematic.

Conductors Contribute to Inductive and Capacitive Behavior

The geometry of each trace in your PCB is responsible for creating parasitic capacitance and inductance in your board. The parasitic capacitance arises because a signal trace is separated from the conductor that carries its return path by the insulating substrate. The parasitic inductance arises because the signal trace and its return path must form a closed loop, effectively creating an inductor. The exact inductance depends on the magnetic permeability of the substrate and the size of the loop in your board. The parasitic inductance is one factor that creates susceptibility to radiated EMI in your board.

Because each trace has some parasitic capacitance and inductance, every trace can exhibit transmission line behavior, regardless of its length. This is not reflected in your schematic unless you build lumped transmission line models for each connection in your schematic. The question of when trace impedance matching should be performed does depend on the length of the trace and any impedance mismatch in an interconnect. I'll address transmission line impedance matching in a later article. For now, just remember that the issue of impedance mismatch can lead to analog signal resonance in your board, or the stair step response seen with digital signals on a mismatched interconnect.

Interior structure of a PCB layout

Fig. 2. The interior structure of a PCB, shown here with vias, helps determine parasitics in your PCB.

This Means Every Trace Acts Like an RLC Circuit

The important point here is that you cannot avoid these parasitics in a real PCB layout, and they are responsible for many signal integrity problems that arise in real PCBs. Analyzing the behavior of real circuits in a PCB requires considering these parasitics in models for real interconnects. These parasitics, the DC resistance of a trace, and the parasitic conductance of the substrate can also contribute to the characteristic impedance of each trace in your PCB. When the parasitic capacitance and inductance of an isolated trace are considered alongside the DC resistance and the substrate's residual conductance, we now have a circuit that behaves much like an RLC circuit when driven with switching digital signals or AC signals. These facts must be considered when analyzing signal integrity problems in your board. A typical interconnect can be modeled using the circuit diagram shown in Fig. 3.

Lumped circuit model

Fig. 3. Equivalent circuit model used to analyze transmission lines. Note that L, G, and C are all related to your substrate properties and layout geometry.

Coupling Between Traces

Parasitics in your board are also responsible for coupling between traces. Coupling is responsible for the following aspects of signal integrity:

  • Capacitive crosstalk: Because neighboring traces are essentially separated by some dielectric, they have some mutual capacitance. This is responsible for capacitive coupling.
  • Inductive crosstalk: Traces that run parallel essentially form two neighboring inductors, thus they have some mutual inductance. A changing current in one conductor can induce a back EMF in the other conductor. This is known as inductive crosstalk.
  • Even/odd and differential/common impedances: Parasitics are responsible for the different impedance values seen in traces, depending on how they are driven. In short, parasitics cause the impedance seen by a signal on a trace to be different from the characteristic impedance.
  • EMI susceptibility: Parasitics allow a noise source in one area of the board to propagate in another area of the board.
  • Cavity resonances at high frequencies: At mmWave and higher frequencies, your board can exhibit cavity resonances, which arise in part due to coupling between various portions of the board. These resonances can be complex (i.e., their frequencies are not always related by integer multiples of some lowest order resonance), and they depend heavily on the board's geometry and dielectric properties.

Coupling can never be eliminated completely from all areas of the board, but you can provide certain groups of traces with different levels of isolation with the right layout and stackup design. Regarding noise immunity, you can reduce common mode by 10's of dB by using differential pair routing where possible. In this case, make sure you carefully match the lengths of your traces within the tolerances specified in your signaling standards.

Just as signals on one trace can create signal integrity problems on another trace, so too can the return path in one part of your board cause signal integrity problems elsewhere in your board.

How Does a PCB Layout Affect Your Return Path and Signal Integrity?

The answer to this question really depends on the frequency content of signals in your board, as well as the trace/component arrangement and your layer stack. Modern PCBs are generally routed over a ground plane, and it is generally assumed that the return current is always induced directly below a signal thanks to the substrate's parasitic capacitance. However, the astute designer will know that capacitive impedance is inversely proportional to a signal's frequency. Therefore, a lower frequency signal will induce less current directly below a signal trace when routed above a ground plane.

So what happens to the return current? Some of the current will appear below the trace, while the rest of the current will spread throughout the board. Once you add multiple components and interconnects in a board, the return path becomes more difficult to predict analytically due to the coupling issues mentioned above. To get an idea of what happens at different frequencies take a look at the images below. These images show the current distribution in a ground plane below a signal trace. An AC signal is launched into the U-shaped trace and flows to the return point through the ground plane.


Return path as a function of frequency in schematic vs. layout

Fig. 4. Return path as a function of frequency. Left: 1 kHz, Right: 1 MHz. These images can be found in Resistive vs. Inductive Return Current Paths by Bruce Archambeault.


In these images, the return current path in the ground plane clearly depends on the signal's frequency. In the DC case (not shown), the current takes the shortest path back to the return point (just a straight line), which is just the path of least resistance. As the frequency increases, more current becomes confined below the signal trace. At 1 MHz, we see the current is spread in the ground plane below the trace. At theoretically infinite frequency, the return current would follow the exact same path as the signal trace.

Because the return path in a PCB depends on frequency, and the loop inductance depends on the entire path travelled by a signal as it returns to ground, the loop inductance for a particular signal path also depends on frequency. In transmission line models, this is normally ignored as the typical assumption is that the signal frequency is large enough that the return current closely follows the path of the transmission line. This creates two problems:

  • Designers that assume the return current always follows below the trace may underestimate the inductance, causing them to overestimate the transmission line's damped resonance frequency and underestimate the characteristic impedance.
  • A transmission line's characteristic impedance will depend heavily on the measurement method. This is already well-known by test instrument manufacturers and substrate material suppliers.

The situation is even worse with digital signals. Because digital signals are essentially a superposition of multiple frequency components, each component will experience different levels of coupling. This means that different frequency components will have different return paths in a ground plane. In addition, a digital signal can excite a transient response in an interconnect thanks to parasitics in a trace, which leads to other signal and power integrity problems that are outside the scope of this post.

This is one reason why differential pairs are often used when possible. This allows the PCB designer to control the return current path in an interconnect; the return current will just be routed in the differential pair. Therefore, the loop inductance in a circuit can be rather accurately estimated, leading to accurate estimates of the differential/odd mode impedance values.

PCB Schematic vs. Layout Summary

In closing, don't think that your PCB will always work as you intended just because your schematic is properly designed. Parasitics are responsible for the following unavoidable aspects of your board's behavior:

  • Resonant behavior of real circuits
  • Differences between calculated impedance and observed impedance
  • EMI susceptibility
  • Coupling between different board sections
  • The real return path in your board

Note that we haven't even considered the relationship between signal integrity and power integrity. The two areas should not be considered in isolation (no pun intended). I'll continue delving into different aspects of signal and power integrity in future articles.


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