PDN Impedance Calculator

Analyze and Verify PDN Performance

This PDN calculator tool is originally based on the PDN Tool V1.1.1 from Altera Corporation. Originally intended for use with Altera FPGA devices, the tool has been generalized to any processor in a PCB that pulls power from a VRM, decoupling capacitor array, and power-ground plane pair.

This tool will help users design a robust PDN for a large processor by determining an optimum number, type, and value of decoupling capacitors needed to achieve a user-defined target impedance (Ztarget) up to the target frequency of interest. The equivalent schematic considered in this analysis is shown below.

PDN Impedance in High-Speed PCB Design

Power integrity problems in a high-speed PCB are usually not caused by a lack of capacitance in the abstract. They come from a PDN whose impedance is too high over the frequency range where the load demands current. That is the point of target impedance. It gives you a design limit for the rail so switching events do not create excessive ripple, ground bounce, jitter, or other behavior that shows up later as a signal integrity problem. In that sense, the calculator is not just estimating capacitor behavior.

This is also why the tool includes more than capacitor value and capacitor count. A real PDN is a broadband network built from the regulator, bulk capacitance, discrete decoupling capacitors, mounting inductance, spreading inductance, plane capacitance, and the connection into the package through balls and vias. Each of those terms dominates over a different part of the impedance spectrum. At lower frequencies, the regulator and larger capacitors tend to matter most. As frequency increases, the loop inductance in the capacitor mounting structure, the BGA escape, and the plane pair begin to control the result. In faster systems, the board and package are not separate problems. They are two sections of the same power delivery path.

The most useful output is the impedance curve relative to the target line. If the curve stays below target, the rail has a better chance of meeting its ripple requirement during transient loading. If it rises above target, the problem is not automatically solved by placing more capacitors. A peak in the curve usually means the network has formed a resonance, and that same behavior will appear in the time domain as a stronger transient oscillation on the rail. In other words, the plot is showing where the PDN is likely to ring, not just where it has too little nominal capacitance.

For high-speed layouts, a good PDN result usually points back to physical design decisions rather than BOM changes alone. Plane spacing, overlapping plane area, via count into the power-ground pair, capacitor package size, and mounting geometry all change the impedance curve in ways that matter more than simply increasing capacitor quantity. That is why PDN design has to be treated as part of stackup design and package escape planning, not as a cleanup step after placement and routing are already fixed.

Determining Target PDN Impedance

The reason we need to limit the PDN impedance below some target is because the magnitude of voltage ripple is related to the magnitude of current impulses drawn by I/Os on fast digital processors. The simple relation between these quantities is Ohm's law, where the PDN impedance is the conversion factor between current impulses and the transient voltage. This is why PDN impedance can be determined with a simple formula, which uses a voltage ripple value as a percentage of the stable core voltage and the peak current drawn by all I/Os running on the chip:

This gives a good estimate of the maximum impedance value that we can accept in the PDN. Any value below this maximum would be expected to produce a transient that, while complex in terms of time-domain complexity, maintains its amplitude within the noise margin for the I/O supply rail. As most processors have multiple rails operating at different voltages and current requirements, the same formula would apply to each rail independently (assuming separate regulators).

Once we have a target impedance design, it is possible to predict the transient response using an inverse Fourier transform, as shown in the formula below. This transform takes the input current pulse in the frequency domain and the PDN impedance spectrum, and the transient voltage can be predicted. Note that we can add a scale factor Veq to set the equivalent voltage to the stable (quiet) level required by the rail.

This is equivalent to take the convolution of these quantities using the impulse response function for the PDN impedance function (Z). Any mathematical scripting language (MATLAB, Wolfram Mathematica, etc.) can perform these calculations in the frequency domain, although the impulse response function approach has largely been taken as the standard approach in EDA software.