RISC-V embedded

PCB Design for FPGA SoMs and Carrier Boards


FPGAs are supporting many advanced applications that require high I/O count, extremely fast interfaces, and specialty logic that cannot be found in off-the-shelf ASICs. Systems that are built with FPGAs can be structured in a variety of ways. For example, some controller boards for applications in radar, IoT, and sensor fusion simply use a single board with an FPGA as the main processor. An alternative approach to this board architecture is to use a system on module, or an SoM, alongside a carrier board. The FPGA can be placed on the SoM, and the carrier board can be designed with the required peripherals for the systems application.

This is a useful design architecture for many applications where future proofing is required, or where peripherals integrate certain interfaces or features that cannot be instantiated in the FPGA interconnect fabric. In this article, I'll give an overview of FPGA SoM designs, the overall architecture of an SoM and its carrier board, and some of the important components that make these systems highly adaptable. Some of the newest applications of these systems are found in automotive, mil-aero electronics, and in advanced sensing or vision platforms.

FPGA SoM Design Architecture

To begin, we need to design a PCB that can support the selected FPGA as well as the primary peripherals that will be implemented on the SoM. In general, systems with an FPGA as the main processor will have high I/O counts with many fast interfaces. This can result in very high layer counts on some PCBs due to the need for controlled impedance on multiple layers, interleaved ground layers for impedance references, and multiple power rails or complete power planes operating at different voltages. For some large FPGAs, it is common to see an FPGA board with 16 layers, or with layer counts reaching up to 32 layers.

Before floor planning the board, it's important to consider the following aspects of the PCB:

  • Layer count and material selection
  • Board size, which can influence placement and thus layer count
  • The number of required high-speed interfaces that will require controlled impedance
  • The number of low speed interfaces and the total signal count in these interfaces
  • How the SoM will attach to its carrier board

Layer Count

The number of required layers can be determined in a few ways. The classic method for doing this is to look at the largest BGA on the board and use the number of row column pairs encircling the edge of the largest BGA to determine the number of required signal layers. You then add in additional layers for ground to support high-speed interfaces and to provide shielding between layers. You may then need to add one to two more layers for power rails, which may be running at multiple voltages.



Large FPGAs will be packaged with fine-pitch BGAs.


One smart practice is to allocate the highest current power rail to its own layer to ensure power Integrity on that rail. If many interfaces will be operating at a lower core voltage that has smaller noise margin, then it is a good idea to also give this lower voltage rail its own layer and use a power plane with an adjacent ground plane.

These steps will help ensure signal integrity and power Integrity in the FPGA SoM design. They will also aid controlled impedance routing by providing clear references for single ended and differential high-speed buses.

High Speed Connectors

An SoM for an FPGA will need some connection mechanism to interface with the carrier board. The most common method for doing this is to use two or more mezzanine connectors that can support high-speed signals. Examples include the Hirose connectors shown below.


FPGA SOM connector

Hirose mezzanine connector examples.


These connectors can typically support high bandwidth signals, with bandwidths reaching to the high GHz range. These connectors can vary in terms of their mechanical reliability, so they should be selected carefully if the SoM and carrier board will be deployed in an environment where mechanical shocks or vibration can arise. Some companies like samtec and amphenol make high-speed connector assemblies specifically for these rugged applications, such as in aerospace and defense electronics.

Another option is to design a castellated module. A castellated module will solder directly to the carrier board. This presents a problem for future proofing and modularity. One advantage of using connectors instead of castellated holes is that an SoM or carrier board can be replaced later when connectors are used for the interface. This design brings an element of future proofing to the device.


FPGA SOM castellated

FPGA SoM with castellated holes around the edge of the PCB. [Source: MYIR Tech]


Another option is an edge connector interface. This is typical if you will be installing the SoM in a PCIe slot in a computer. In fact, PCIe lanes will most likely be the standard interface used to access the FPGA in this type of deployment. Typical applications include network processors or high-speed interface cards, AI accelerator cards for data centers, and specialty sensor or instrument interface cards.

Should Pin Headers Be Used?

An interface that should not be used between an SoM and a carrier board is pin headers. Simple pin headers, as through-hole devices, might create signal Integrity problems when excited with very fast signals, and they may not be appropriate for creating a controlled impedance interface in a high-speed channel. Surface mount connectors are generally preferred for this purpose.

However, pin headers can still be used on the carrier board or on the SoM for other purposes, such as the programming interface or to connect to other devices in the final assembly. In this case, the pin headers are generally placed on the carrier board rather than on the SoM in order to ensure that the SoM has a slim profile.



Commercially available FPGA SoMs. Tall components like pin headers are normally omitted to ensure the SoM has a low profile. [Source: Sundance Technology]


Bringing in Power

One important point to note for the overall system is how power is brought into the SoM and the carrier board. It is generally preferred to bring power into the carrier board and then distribute it to other components, as well as to the SoM through its connector interface.

This means that the carrier board will need to have power regulation on it in order to take a potentially unregulated power source and regulate it to the required voltage for peripherals and critical components on the carrier board. If the FPGA operates at the same rail voltage as on the carrier board, it is actually recommended to provide additional regulation directly on the SoM.

The reason for this is that you need to ensure there is always a low impedance path from the regulator module to the power inputs on the FPGA this is best provided by taking the unregulated input providing it to the FPGA through the SoM and its connector, and regulating it on the SoM with additional circuitry. This is an important part of power integrity, it ensures that power being pulled from power-ground plane pairs can be supplied to the FPGA power pins with the lowest possible impedance, and thus a strong transient response on the power rails can be prevented.

Carrier Board Design

If you're designing an SoM, and you intend it to be used in an end product, you'll generally need to design the carrier board as well. The reverse is not always true. SoMs are available as evaluation/development products, or as open source projects, and the design task becomes to build a carrier board that mates with the SoM’s pinout. The carrier board’s mechanical constraints need to accommodate the FPGA SoM design. These design tasks can require significant collaboration among multiple design disciplines, and an experienced design firm can help you navigate to the complexities of these products.


NWES is an experienced PCB design firm that develops FPGA SoMs and carrier boards for advanced digital systems. NWES helps aerospace OEMs, defense primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology. We've also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we'll make sure your next high speed digital system is fully manufacturable at scale. Contact NWES for a consultation.


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