The term "signal integrity" is thrown around a bit and sometimes can seem like an esoteric idea, especially when we refer to a signal integrity simulation. This begs the question: what exactly needs to be examined in a signal integrity simulation?
In PCB design, signal integrity becomes a different beast as boards can get very complex. Your design tools tend to offer a lot of options for pre-layout and post-layout signal integrity simulations, but it can be difficult to see exactly which signal integrity simulation tasks and analyses are necessary for your PCB layout. Some of the basic signal integrity simulation tools in high-quality layout software will give you some significant insight into signal behavior and will help you qualify your design before manufacturing. Here’s which analyses you should perform before and during the PCB layout phase, and what you can learn about signal behavior in your system.
There is no single signal integrity simulation you can perform that tells you everything about your board. Rather, there are multiple analyses you’ll need to perform to qualify different aspects of signal behavior. Signal integrity simulations can be broadly divided into pre-layout and post-layout simulations. A pre-layout signal integrity simulation will occur in the schematic using a SPICE-based simulator, while a post-layout simulation will occur in the PCB layout. These post-layout simulations may be performed analytically or using an integrated field solver; most high quality post-layout or design signoff tools use an integrated field solver for signal integrity simulations, which run in the background and require zero configuration. More powerful post-layout simulations are generally not meant for signal integrity. Instead, they are used for multiphysics simulations, such as electrical-thermal co-simulation.
Your schematic cannot account for parasitics, which are determined by your specific layout of components and conductors on your PCB layout. However, it can show you how different circuits affect signal behavior. This is an important aspect of component selection and signal planning as you can see directly how different components distort signals in the time domain or in the frequency domain.
The exact simulations you should perform depend on whether you have linear or nonlinear circuits. With linear circuits, you can use standard SPICE techniques in the time and frequency domain. Here are the basic time-domain and frequency-domain signal integrity simulations you should perform in your schematic.
Pre-layout simulations you should perform in the time domain and frequency domain for linear circuits.
Nonlinear circuits can also be simulated with a standard SPICE engine in the time domain. You can also work in the frequency domain directly, but it requires a small-signal analysis, and you won’t see how . Here are the basic time-domain and frequency-domain signal integrity simulations you should perform in your schematic.
Pre-layout simulations you should perform for non-linear circuits.
Note that certain analyses are only defined for linear time-invariant circuits. An example is transfer function calculations. For nonlinear circuits, transfer functions can only be properly calculated using small-signal analysis, but you won’t see any harmonic generation or mixing in this approximation, so the results will be incorrect. For time-varying circuits, you’ll have to work in the time domain except in certain circumstances (e.g., the time-variance is harmonic). Although you may be limited in the pre-layout simulations you can perform, you can still learn a lot about the interaction between your circuits and your signals. I’ve talked about signal integrity, but the same ideas apply to power integrity simulations for digital and analog signals.
Perhaps the two most important post-layout signal integrity simulation and analysis tasks are crosstalk and reflection simulations, particularly with broadband digital signals. For crosstalk, the strength of a signal coupled onto a victim line will depend on the exact layout on a PCB as this is a parasitic effect. A broadband digital signal with fast edge rate can create a strong crosstalk signal, even though the clock rate may be very slow. Your goal should be two-fold:
Reflection is all about determining whether an interconnect, source, and load are impedance matched. When there is an impedance mismatch, there will be a reflection at the impedance discontinuity. Impedance matching with broadband signals can be problematic when dispersion is considered in impedance controlled design. For analog signals, the situation can be quite different as you may only be working at a single frequency, and you only need to worry about impedance matching at a single frequency. If you can perform a parameter sweep, you can examine how your termination network influences the time-domain signal. Altium Designer and OrCAD/Allegro have this functionality included in their signal integrity simulation tools.
At NWES, we’re specialists at designing high speed and high frequency PCBs, and we know how to get the most use out of signal integrity simulation tools when creating PCBs. We work with electronics companies to design modern PCBs and create cutting-edge technology. We've also partnered directly with EDA companies and several advanced PCB manufacturers, and we'll make sure your next layout is fully manufacturable at scale. To see how we can help you with your next design, contact NWES for a consultation.