Bypass capacitors and are critical for combating a specific power integrity problem called ground bounce (also called simultaneous switching noise, simultaneous switching output noise, or power bounce). Choosing the right bypass capacitor size is only half the solution to this particular problem. Bypass capacitors also need to be placed in the right location on your board. If you place these circuit elements in the right location, you can greatly suppress ground bounce in your integrated circuits.
Ground bounce is one of those esoteric aspects of power integrity and PCB design that requires understanding something about the internal structure of transistors and logic circuits. Once this portion of the problem is clear, the best location to place a bypass capacitor should be obvious. Let’s take a deeper look at the causes of ground bounce and proper bypass capacitor placement in your PCB.
Ground bounce refers to a change in the voltage level between the output of a driving IC and the PCB ground plane. In other words, the IC is designed to have an output of +5 V when measured with respect to the PCB ground plane, but ground would cause you to measure something less than +5 V between the output and the PCB ground plane. Ground bounce is a parasitic effect that occurs when an IC switches, similar to ringing on your PCB’s PDN.
In a real IC, there is some parasitic inductance between the PCB ground plane, IC pad/pin, packaging and bond wire, and the PCB ground plane. The parasitic inductances from these elements are in series. When the IC switches, the sudden inrush of current into the IC causes a back EMF to develop across these parasitic elements, which points from ground towards the output. In other words, the output voltage between the IC output and the PCB ground plane is lower than the design value. Even as ICs have become miniaturized over time, they can still experience significant ground bounce due to the back EMF created in the IC due to parasitic inductance, simply because ICs have been switching with higher edge rates.
This power integrity problem is quite different from transient ringing on the PDN of your PCB. The transient ripple in a PDN is caused by parasitic capacitance and inductance in the PDN layout, and the magnitude of the voltage ripple is proportional to the current drawn by a switching IC and the impedance of the PDN.
A bypass capacitor is a capacitor that is specifically sized and placed to eliminate ground bounce. First, one should note that the term "bypass capacitor" does not refer to a special type of capacitor; any type of capacitor could theoretically be used as a bypass capacitor. The same goes for decoupling capacitors; they are not a specific type of capacitor, and any type of capacitor could be used as a decoupling capacitor. Both terms refer to the function of these components and their intended effects on power integrity.
The graphic below shows a circuit model with a bypass capacitor (CB) connected between the Vdd and GND pins on an IC. The inductances in this circuit model (L1-L5) are parasitic elements. In particular, L1 produces a back EMF between the IC die ground plane and the output pin.
Circuit model showing development of ground bounce in a CMOS circuit.
A bypass capacitor does not "bypass" anything in the sense of integrated circuit design. Instead, its function is to compensate certain voltage fluctuations. The specific voltage fluctuation that must be damped with a bypass capacitor is ground bounce, which is associated with the edge rate in a switching IC (I’ll get into this more later). In this model, the bypass capacitor must provide sufficient output voltage to compensate for ground bounce. Ideally, the bypass capacitor will output exactly the ground bounce voltage V(GB). Because the bypass capacitor, PDN, two output transistors, and ground plane form a complete loop, one can see that the voltage across CB opposes V(GB).
The location of a bypass capacitor will cause the signal it outputs to experience some parasitic inductance, as one can see in the above circuit model. Your goal should be to place the bypass capacitor such that this parasitic inductance is minimized. As trace inductance is normally defined on a per-unit-length basis, this means you need to place the bypass capacitor as close as possible to the target IC.
Best options for placing bypass capacitors.
There is another aspect to this that is quite important, which is avoiding a trace all together; this is shown in both cases above. A better choice is to connect your bypass and decoupling capacitors directly to the power and ground planes, rather than to route a short trace on the surface layer. This reduces the inductance for this signal path by approximately a factor 10. In other words, your typical trace on the surface layer, with about 0.5 nH per inch of inductance, would produce a voltage droop of anywhere from 10-100 mV, depending on the output signal rise time. If you take this into consideration, the trace length to the power pin would need to be 20 mils to bring voltage droop within acceptable limits. This is simply not practical.
Instead, you can connect these capacitors directly to power and ground planes. This will provide the absolute lowest possible inductance for power compensation, which will minimize voltage droop as the capacitor charges/discharges to compensate ground bounce.
Typical arrangement of decoupling and bypass capacitors to compensate PDN ripple and ground bounce.
A decoupling capacitor and bypass capacitor are fundamentally sized differently. A decoupling capacitor is generally sized to compensate transient ripple on the PDN, while a bypass capacitor is intended to combat the back EMF due to ground bounce. The size of the bypass capacitor is less important than its self-resonance frequency. If you look at the impedance spectrum of a PDN, the complicated resonance structure arises from the PDN geometry, the types and sizes of bypass/decoupling capacitors used, and the sizes of the different capacitors.
Decoupling capacitors tend to be rather large, so they tend to have a smaller self-resonance frequency. This is fine as any transient ripple on the PDN tends to have narrow bandwidth and tends to have lower frequencies than the signal knee frequency. I often recommend trying to size a decoupling capacitor to provide capacitive impedance up to the knee frequency, but this is not possible in all cases, especially when working with high speed digital signals. This is where a bypass capacitor comes in. The bypass capacitor generally has a smaller capacitance than a decoupling capacitor on the same PDN, but the self-resonance frequency should be higher than the knee frequency (for digital signals) or the signal operating frequency/bandwidth (for analog signals). For digital signals, you can use the following approximation as a lower limit for sizing a bypass capacitor:
Lower limit for the self-resonance frequency of a bypass capacitor when compensating ground bounce in a digital IC.
Be sure to check your component datasheets when selecting a bypass capacitor. Component manufacturers typically provide some values for multiple bypass capacitors required to ensure signal and power integrity.
The typical arrangement of decoupling and bypass capacitors shown above should not always be taken literally. In particular, the use of decoupling and bypass caps in a specific order moving away from a component is a relic of decades past and is not applicable in modern high speed PCB design. In a modern design, the placement of capacitors doesn't matter as long as the PDN is composed of neighboring power and ground planes. In this way, the planes act like a big capacitor and perform much the same function as a combination of bypass capacitors and decoupling capacitors. In addition, the generally low parasitic inductance of the parallel plane layers ensures the self-resonance frequencies (from the circuit theory and cavity resonances) of the plane arrangement are very large (generally ≥100 MHz).
Because charge can be drawn directly from plane layers rather than from capacitors, the order in which decoupling capacitors are placed around the board is less important. I prefer to place bypass capacitors specifically next to the component they are intended to protect from ground bounce simply to prevent parasitic inductance from making ground bounce worse and to provide some extra charge for compensation. Regarding decoupling capacitors, some well-known designers will state you can place them wherever you like. However, I would preface this by saying this is only true as long as the PDN impedance is flat within the relevant signal bandwidth. Parasitic inductance will cause the self-resonance frequencies of capacitors to move to lower frequencies, but this won't matter if your PDN impedance is low enough.
If you’re building an advanced digital system or high frequency analog system, you need a design firm that has experience these systems and much more. Aside from bypass capacitor placement, ground bounce, and other finer points of electronics design, our team of PCB layout engineers and technology researchers will ensure your next product operates as designed and is fully manufacturable. Contact NWES today for a consultation.