The miniaturization trend seen in integrated circuits has forced PCBs to keep up, ultimately leading to HDI designs for common products. Most consumers may not realize this, but they probably own multiple products that rely on HDI design and routing on a PCB. Successful layout and routing in these products relies on designing the right HDI PCB stackup.
Although any board with high layer count will be costly, these products keep up with the trend of packing more advanced functionality into a smaller space. With Tara Dunn’s recent announcement of 1 mil (25 micron) trace widths, HDI designs are getting pushed even smaller, and the limiting factors determining routing density are layer count, net count, and component count. If you’re designing advanced products that push the envelope of component and routing density, pay attention to your HDI PCB stackup before you start your layout.
I’ve seen some questions asked on forums and by other designers that all boil down to this: how many layers are used in an HDI PCB? There is no specific number. My team has used an HDI PCB stackup and routing in boards ranging from 8 to 24 layers and everything in between. The exactly layer count relies on the trace density you need, the total number of HDI nets, and the approximate space they will take up in your board.
You might also need to make room for other components that do not necessarily require HDI routing and that need to be separated from your HDI circuit blocks. An example design we completed recently used multiple wireless protocols in one region of the board separated from the digital section, which was built around a large FPGA. The RF section used relatively wide traces and plenty of ground pour for isolation, while the digital section require routing of over 1000 nets and over 300 components in multiple layers.
With such high net counts being typical in HDI boards, how can you determine the number layers you need in your HDI PCB stackup? Assuming you’re using time-tested HDI manufacturing processes, you need to estimate how many traces will fit onto your board size per layer, then add additional layers for your power and ground planes. For the 1000 net board I mentioned above, we assumed a 10 layer board as an initial estimate for our HDI PCB stackup. Assuming 10 total layers, you can calculate the thickness per layer and use this to determine the trace width you need for controlled impedance. Your own process for estimating a layer count for an HDI PCB stackup could proceed under the following process:
A 14 layer HDI PCB stackup created in Altium Designer. Note the use of skip vias between layers 1 and 3, and between layers 12 and 14, which should have aspect ratio smaller than ~2:1 to ensure reliability under repeated thermal cycling. If the board becomes very dense, the internal buried vias may need to be replaced with stacked blind/buried microvias to provide HDI routing to any layer.
Fine-pitch BGAs are one of the reasons some designers are forced to work in the HDI regime. Getting an estimate of nets per layer is a bit difficult as you need to have the HDI region in your board specified ahead of time, and your BGA breakout and escape routing strategy will constrain your net count per layer. Fortunately, BGA breakout patterns are created in a kind of "grid" pattern with a fixed number of traces per layer, depending on where these traces will fanout. This is the case for traditional dogbone fanout and tented microvia-in-pad fanout strategies. You can usually pull 2 rows of pads from a high density BGA at a time, or possibly 3 if you use very narrow traces.
A dog bone fanout strategy on the surface layer is appropriate for coarse to intermediate pitch BGAs. In the case of extremely fine pitch BGAs with very high pin count, you have no choice but to use blind microvias to reach inner layers as part of your fanout, and you’ll be forced to use a higher layer count in your HDI PCB stackup. This is because of the constraints on the net count per layer, and this applies even if the overall pin count on a fine-pitch device is low.
For differential pairs, you also need to keep traces coupled beneath the BGA package. In protocols like PCIe or DDR, which use differential pairs, it’s easy to reach the outer two rows in the BGA directly on the top signal layer. For the internal layers, you can use microvias with dogbone fanout or microvia-in-pad to ensure neighboring traces stay coupled. Always make sure to include the appropriate anti-pad diameter when routing through plane layers in your HDI PCB stackup. Also try to mirror any bends in both traces on a differential pair in order to maintain symmetry and coupling. If you have a coarse pitch package and very thin traces, you might be able to route a differential pair between pads, rather than placing pads between traces in a pair.
The differential DDR4 data lines on this BGA are too wide to route between balls on the BGA, unlike the case for some PCIe packages. Therefore, the designer will need to add an internal layer to touch groups of balls deeper into the BGA.
Just like any other design, you should check with your fabricator to make sure you're following their DFM guidelines before you create your HDI PCB stackup or begin your layout. There are a number of PCB manufacturers that are highly specialized in HDI PCB fabrication and assembly, and they can accommodate very high layer counts with very thin, very dense traces. Doing this important work first can help save you money on your manufacturing run and helps ensure higher yield.
At NWES, we help electronics companies create high speed, high frequency, and high density PCBs for a variety of applications. We know how to create an HDI PCB stackup to keep your designs operating properly while also helping you stay within budget. We're here to help electronics companies design modern PCBs and create cutting-edge technology. We've also partnered directly with EDA companies and advanced PCB manufacturers, and we'll make sure your next layout is fully manufacturable at scale. Contact NWES for a consultation.