Getting Started With This Edge Card Template

This template provides a board outline and pinout for designing PCI Express (PCIe) expansion cards. It includes mechanical keying and AC‑coupling capacitor footprints so that designers can concentrate on routing the high‑speed lanes. The template conforms to the PCIe x16 standard and can be downscaled to x1, x4 or x8 cards by leaving unused lanes unpopulated.

What The Template Provides

The items below summarize the assets provided by the template. They ensure that the mechanical and electrical aspects of your design adhere to the PCIe specification.

• Board outline and keying – The card edge outline follows the PCIe specification, including the notch locations and mechanical key. This ensures your board will fit correctly in a motherboard slot and prevents improper insertion.
• Pinout tables – The template lists pin assignments for each lane, power rail and control signal. Important pins include +12 V, multiple grounds, SMBus, JTAG, reference clock, and differential TX/RX pairs. Use only the number of lanes you need and leave unused pins unconnected.
• AC‑coupling capacitor pads – Pads are provided near the edge connector for the series capacitors required on each differential pair. Place capacitors close to the connector to minimize reflections and maintain signal integrity.

Using The Template

Applying the template correctly involves mapping your circuitry onto the provided pin assignments and routing high‑speed lanes with proper impedance. Follow these guidelines to avoid common pitfalls.

• Import into your CAD tool – Add the outline and pin definitions into your project and assign net names to each pad according to the lane ordering. Reserve pins for SMBus, JTAG and the reference clock as defined in the specification.
• Designing the stack‑up – Select a stack‑up that supports 50 Ω single‑ended and 100 Ω differential impedance. Four‑layer boards with ground and power planes are typical for PCIe; ensure the signal layers above a continuous plane to control impedance.
• Differential pair routing – Route each TX/RX pair as a tightly coupled differential pair. Keep lengths matched within ±5 mils and use serpentine meanders if necessary. Place AC‑coupling capacitors within a few millimeters of the card edge.
• Power and ground strategy – Provide decoupling capacitors for the +12 V and 3.3 V rails near the edge connector. Use split grounds to separate chassis ground (connected to bracket fingers) from system ground; join them through a resistor or capacitor to control common‑mode noise.

Unique Design Notes

The considerations here are meant to help you adapt the template to different lane widths and ensure reliable operation at all PCIe generations.

• Mechanical flexibility – The x16 template can be shortened to x1 or x8 by trimming the board and removing unused lane footprints. Make sure to maintain the key location so the board still fits in the slot.
• Impedance control – Use controlled dielectric materials and precision trace widths to achieve the required 85–100 Ω differential impedance. Maintain at least 0.5 mm clearance between edge fingers and copper pours to avoid exposed copper and to meet spacing guidelines.
• Reference design for new engineers – This template acts as a starting point for anyone unfamiliar with PCIe. By providing the outline, pinout and coupling capacitor locations, it shortens design time and reduces the chance of mechanical or electrical errors.

By starting with this template, you can build expansion cards for GPUs, network adapters, or custom accelerators with confidence.

When designing a PCIe card, remember that the edge fingers must be plated with gold to endure repeated insertions, and the connector pads should be beveled to ease insertion. Use at least 1 oz copper for the power layers to reduce voltage drop at high currents. Always consult the PCI‑SIG specification for the latest pin assignments and mechanical drawings, as new generations may introduce additional pins for sideband signals or auxiliary power. Performing signal integrity simulations on the differential pairs and reference clock paths helps verify that impedance and insertion loss targets are met before fabrication.

Additional Resources

Read the full guide article on Altium Resources for a deep dive on this project. The video below shows how the edge card template conforms to the PCIe standard and how the design can be expanded to an x32 lane design as needed.