Back in the 1980’s, design issues like impedance control, termination, control over parasitics, and unique interconnect architectures were something of an afterthought. According to the great Rick Hartley, designers at the time were placing band-aids on their boards; they were doing little to understand the complex signal integrity problems that arise from uninformed routing decisions.

Fast-forward to today’s high speed/high frequency data center environments, upcoming 5G architecture, high performance computing, and other applications at high speeds/high frequencies. If you look at the routing specifications used in these applications and with many high-performance SOCs, you’ll find that these devices make copious use of differential pair routing with impedance control throughout the board. Even single ended signaling, such as the parallel lanes in DDR, still requires precise impedance control to prevent reflections. This puts impedance control in PCB design at even greater importance and brings it into the mainstream.

With single-ended impedance controlled traces, you need to carefully adjust the trace thickness, width, and distance from the reference plane in order to keep the impedance at a constant value. In a perfect world, we would only worry about the impedance of the trace, but in reality there could be any number of elements that create impednace discontinuities which would contribute to reflection and potentially noticeable ringing:

• Vias and antipads on layer transitions
• Non-functional pads on vias
• Leftover stubs on through-hole vias
• Nearby pads along a transmission line
• The structure of the load's input impedance

The same idea applies to differential impedance control in PCB design, but you need also need to account for the spacing between traces as this defines the differential impedance (and thus the spacing between elements along each trace that create impedance discontinuities). In other words, you need to adjust the characteristic impedance of each line in the pair, as well as the coupling between pairs in order to hit a target differential impedance.

This process can be difficult with differential transmission lines unless you know the coupling coefficient (i.e., mutual capacitance and inductance) for the two lines in the pair. However, for single-ended microstrip or stripline transmission lines, you can use Wadell’s equations for the characteristic impedance alongside the approximate propagation delay, impedance in terms of parasitics, and propagation constant from the Telegrapher’s equations to size trace dimensions to maintain impedance while minimizing noise sources.

Example with Microstrip Traces

Let’s take a look at an example with single-ended microstrips and striplines. I’ll run through an example with microstrips, but you can take the same approach with single-ended striplines. To start, we need an accurate equation for the impedance of a single-ended microstrip trace. Wadell’s equations are widely regarded as the most accurate analytical equations for describing the impedance of single traces and coupled traces. For microstrips, the lossless characteristic impedance is:

 

 

Next, we can convert this characteristic impedance into a lossy impedance by including the standard circuit elements in the transmission line impedance equation derived from the Telegrapher's equations:

 

 

It is Eq. (2) that can be used to describe characteristic impedance and can be used as the objective function in a design optimization problem. Finally, we need a model to describe the copper roughness factor K, or a measurement of this function for the material set being used in the design. This is probably the most difficult part to determine to high precision up to high frequencies because it is morphology-dependent. Research into this has been ongoing by many industry experts.

Your goal in ensuring impedance control in PCB design is to minimize deviations from the target impedance within the required signaling bandwidth. This requires identifying the deviations in impedance along an interconnect, which could be due to parasitics along the line, or impedance deviations from vias/pads/stubs within the interface's bandwidth requirement.

This is a reasonably complex nonlinear optimization problem with three variables (the trace dimensions) and two constraints. One of these constraints is that the characteristic impedance be held constant, while the other depends on the ratio of the width of the trace to its height above the substrate (see Eq. (1)). This type of problem may be amenable to gradient descent methods, although my preferred method for this type of problem is to use an evolutionary algorithm. This type of algorithm is slower than gradient descent methods (e.g., generalized reduced gradient), but it is adaptable to strongly nonlinear problems. It can also be customized as a self-adaptive optimization algorithm, where the algorithm chooses among different population generation strategies as the algorithm runs.

• Read more about this transmission line optimization problem in this article.

 

Impedance control in PCB design can be difficult if you do not have the right tools and experience, and the same goes for transmission line ringing reduction. If you’re looking for a knowledgable firm that offers cutting-edge PCB design services and technology research services for innovative electronics companies, contact NWES for a consultation.

 

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