HDI PCB manufacturing is distinguished by two very important processes, or rather groups of processes. These are sequential lamination and plating processes for forming blind and buried vias. These two processes, along with mechanical or laser drilling, are essential for fabricating an HDI PCB in one of the standard stackup configurations. Process engineers in the manufacturing sector plan out HDI builds based primarily on the layer build-up order defined in a sequential lamination process.

Overview of Sequential Lamination

Sequential lamination is utilized in the manufacturing of HDI PCBs to achieve high layer counts and complex interconnections. This process involves multiple cycles of lamination, stacking, and bonding subsets of layers to build up the final PCB structure. HDI boards, which utilize blind and buried vias for layer interconnections, require this process to maintain precision and reliability due to the high density of the connections.

The sequential lamination process in HDI manufacturing includes several key steps:

Initial core preparation:

• Fabricate the initial core, usually a double-sided PCB with through-holes which will act as the buried core vias (e.g., Type I or II HDI stackup)
• Define initial traces and pads through imaging and etching processes

First lamination cycle

• Apply a dielectric layer to the core
• Drill microvias in the dielectric layer using laser or mechanical drilling
• Metallize the microvias through electroless and electrolytic plating to form electrical connections

Stacking and bonding:

• Stack additional layers of copper foil and prepreg (a fiberglass cloth impregnated with resin) on the core
• Bond these layers together under heat and pressure in a lamination press
• Repeat the drilling, metallization, stacking, and bonding process for each layer set

Final processing:

• After all lamination cycles are complete, drill through-holes
• Complete outer layer imaging, etching, and plating

 

 

Considerations for Sequential Lamination

Sequential lamination allows for higher layer counts and denser interconnections. PCB designers can achieve more complex routing and higher component densities by leveraging this process.

Optimal number of lamination cycles: Determining the optimal number of lamination cycles is essential to balance manufacturability and design complexity. Excessive cycles can introduce risks of misregistration and potential failure of via structures.

CTE Mismatches: The CTE mismatch between different materials can lead to stress and potential delamination. Designers need to consider materials with matched CTE values to ensure reliability.

Minimizing delamination and resin cracks: Using materials with good adhesion properties and controlling the lamination parameters can minimize delamination and resin cracks. Pre-conditioning of materials and careful handling during the process are also important.

The ability to use microvias, blind vias, and buried vias influences placement and routing strategies. Designers will mix these available via options based on the type of standard HDI stackup they wish to use. A group of 4 standard HDI stackup options is listed below.

 

 

Design for Manufacturability (DFM)

Sequential lamination impacts DFM guidelines, as designers need to ensure that their designs are manufacturable within the capabilities of the lamination process. This includes considering the minimum spacing, alignment tolerances, and potential stress points on via structures.

The choice of materials for the dielectric layers and core impacts the lamination process. Designers must select materials that are compatible with the lamination process and drilling process (e.g., laser-drillable pre-pregs), as well as provide the necessary electrical and mechanical properties. Sequential lamination in HDI manufacturing allows for the creation of complex, multi-layered PCBs with high interconnection density, impacting various design decisions to ensure manufacturability and reliability.

Plating Techniques

In HDI PCB manufacturing, plating techniques are employed to establish reliable electrical connections through microvias, blind vias, and buried vias. These techniques ensure that vias are properly metallized to form robust interconnects between different layers of the PCB.

Electroless Copper Plating

Electroless copper plating is used to deposit a thin, uniform layer of copper onto the walls of drilled vias. This process involves immersing the PCB in a chemical solution that facilitates the deposition of copper without the need for an external electric current. Electroless copper plating provides a conductive base layer inside the vias, which is essential for subsequent electroplating processes. This thin layer ensures uniform coverage and reliable electrical connectivity.

• Clean and activate the via walls using a pre-treatment process
• Immerse the PCB in an electroless copper plating bath to deposit a thin seed layer of copper inside the vias
• Rinse and dry the PCB to prepare it for subsequent electroplating

 

 

Electroplating Techniques

Electroplating is the process of depositing additional copper onto the vias to achieve the required thickness for electrical and mechanical reliability. There are several techniques used in HDI manufacturing:

Wrap Plating

Wrap plating involves electroplating copper around the hole walls and extending onto the surface foil.

• After electroless plating, the PCB is immersed in an electrolytic plating bath
• Apply an electric current to deposit copper on the via walls and surface pads

Thickness: Wrap plating typically deposits 0.3 to 0.6 mil of copper, depending on the required specifications.

Impact on Design:

• Ensures a robust connection between layers by wrapping copper around the via and onto the surface pad
• Influences the minimum feature sizes that can be reliably etched on the surface due to the additional copper thickness

Button (Spot) Plating

Button plating deposits copper specifically in the via holes and on the pads, avoiding unnecessary copper on the entire surface.

• Apply a plating resist to cover the entire PCB, exposing only the via locations and their associated pads
• Electroplate copper to achieve the desired thickness within the vias

Impact on Design:

• Minimizes the amount of excess copper on the PCB surface, simplifying subsequent etching processes
• Provides precise control over copper thickness in the via barrels, enhancing via reliability without affecting surface features

Via Fill Process

The via fill process is used to fill drilled vias with conductive or non-conductive materials after plating, ensuring a flat and planar surface for further PCB processing.

• Clean the drilled vias using plasma etching to remove debris and resin smear
• Apply a conductive or non-conductive fill material into the vias
• Cure the fill material to harden it and create a solid plug within the vias
• Planarize the filled vias to ensure a smooth surface

The via fill process ensures that vias are properly filled and planarized, which is crucial for achieving reliable interconnections and a flat surface for component mounting. Planarization is very important for finer pitch BGA packages as nonplanarity can lead to defects in the solder balls on BGAs.

Via-in-Pad Design

Plating techniques allow for the use of via-in-pad designs, where vias are placed directly beneath component pads. This design approach increases component density and reduces signal path lengths. Designers must consider the manufacturability of via-in-pad structures, ensuring that plating and filling processes are optimized to avoid reliability issues such as voids or insufficient copper thickness.

Component Density and Routing

Advanced plating techniques enable higher component densities and more intricate routing on HDI PCBs. Designers can place components closer together and route signals through multiple layers without compromising reliability. The choice of plating technique influences the achievable trace widths and spacings, impacting the overall design layout and electrical performance.

Process and Chemistries Determine Reliability

Properly executed plating processes enhance the mechanical and electrical reliability of vias, reducing the risk of failures in the field. These processes impact design decisions by enabling high component densities, ensuring robust interconnections, and influencing the overall layout and performance of HDI PCBs. Designers must work closely with manufacturers to ensure that the selected plating techniques meet the specific requirements of the HDI PCB, balancing performance, manufacturability, and cost considerations.

Available plating techniques and chemistries for HDI and ultra-HDI (UHDI) PCBs are still evolving. The need for new chemistries is due to reliability issues with materials, their shelf life, and whiskering over long-term operation. As these more advanced plating chemistries become commercialized, we will bring you these advances and describe how they affect the engineering approach in HDI and UHDI PCB design.

 

Whether you're designing high-speed PCBs for mil-aero embedded systems or a complex RF product, you should work with a design and development firm that can ensure your product will be reliable and manufacturable at scale. NWES helps aerospace OEMs, defense primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology, including power systems for high reliability applications and precision control systems. We've also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we'll make sure your design is fully manufacturable at scale. Contact NWES for a consultation.

 

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