Differential pair routing

Secrets of Differential Pair Routing in High-Speed PCB Design


As an analog or RF designer, you might not realize the importance of differential pairs until you start working with high-speed digital signals. High-speed interfaces are routed using differential pairs. Differential pairs provide many advantages over single ended traces, particularly in terms of their noise emission, ability to withstand common mode noise, and immunity to high ground offsets.

In fact, it was the large ground offset issue and their lower level of noise emission that led to their use in routing between communications equipment. Although this was the original justification back in the 1980s, similar points apply today in advanced PCB layouts, where high-speed signals can experience significant degradation during routing. The challenges involved in correctly routing a high-speed different pair relate to setting the required impedance, ensuring signals are correctly read at the receiver, and finally, floorplanning to ensure enough spacing is available to prevent crosstalk.

In this article, we’ll look at some differential pair routing guidelines and best practices, as well as some specific signal integrity problems that these can help solve. One important aspect of differential pairs is the need for symmetry and length tuning, which is sometimes misunderstood and needs clarification. Some guidelines call for things like strong coupling without correctly explaining what this actually means. Designing and routing differential pairs correctly also requires an understanding of impedance and its relation to PCB stackups and termination at a receiver. We’ll get an initial view of these aspects of differential pair routing in this article.

It Starts With Differential Impedance

All differential protocols will have a specified impedance target for differential pairs that is found in the high-speed digital protocol’s signaling standard. There is also a single ended impedance target that will be specified for a given interface. This is sometimes confused with the characteristic impedance, However the single ended impedance may not be the characteristic impedance due to the coupling strength between the 2 traces in a differential pair.

Characteristic Impedance vs. Odd-mode Impedance

The single ended impedance of a trace in a differential pair is actually the odd mode impedance. It's often stated that the traces in a differential pair must always be spaced close together. In this case, the electromagnetic coupling between them will create large mutual inductance and mutual capacitance. This will cause the single ended impedance of a trace in the differential pair to be different from the characteristic impedance. This is something that happens whenever there is strong parasitic capacitance between conductive elements in an electronic system.


Differential pair routing width

This graph shows the trace width required for a differential pair to have 100 Ohm differential impedance/50 Ohm single-ended impedance as a function of spacing and substrate thickness.


This is important because, when designing the traces in a differential pair, one cannot use the width that gives a target characteristic impedance and expect to hit the single-ended impedance value if the pairs are spaced too close together. The single-ended impedance specification matters for termination, while the differential impedance specification is only a shortcut to the single-ended impedance value. Depending on the interface (e.g., USB), you could route the traces apart from each other as long as the single-ended impedance matches the characteristic impedance.

Once impedance is understood and correctly calculated, it can be used to determine the propagation constant. This will then determine losses, S-parameters, and the need for length tuning along the interconnect. Finally there is also termination to consider as this relates directly to the single ended impedance for each trace.


The typical image showing a parallel termination resistor applied at the inputs of a differential receiver is over simplified and is only a limited case of real differential receiver circuits. These circuits are more complex crossing detector circuits; they trigger a change in the logic state when the two opposite polarity signals cross over each other in the time domain during their rising/falling edges. An example differential receiver circuit is shown in the image below.


Differential pair routing termination

Example LVDS driver and receiver termination circuit. This type of circuit would be implemented on-die.


Obviously, these circuits will be more complex once we consider more advanced signaling standards that include equalization in the receiver (e.g., PCIe Gen 5, GDDR5, high-Gb Ethernet…). However, the main functionality of the receiver as a crossing detector is the same regardless. This circuit will source or sink some current based on any mismatch between the 2 signals that arrive at the receiver. This is how they compensate for any mismatch. As long as they cross at any level during the rising edges within the high/low threshold levels, then the 2 signals can trigger a change in the logic state in the downstream logic circuit.

Length Tuning

While it is true that the receiver circuit can compensate for some length mismatch, it is best practice to simply match the lengths as close as possible. There are good reasons for this. First, we would like to minimize skew and ensure that common mode noise is minimized at the receiver. It is also very easy in modern CAD tools to simply match the lengths of traces in the pair whenever possible. CAD programs make it very easy to do this by automatically applying length tuning sections to a trace when a mismatch is triggered by the DRC engine in your CAD software. This means some floor planning and skew calculation should occur before any differential pair routing is performed.


Length tuning in differential pair routing

Length tuning sections in a differential interconnect.


Differential Pair Routing in a PCB

Based on the above facts regarding differential in differential interfaces we can deduce some simple guidelines that help insure maximum noise reduction. Noise reduction in a high-speed PCB as well as the ability to withstand ground offsets are the two main advantages of differential pairs in electronics systems. When routing the pair it is important to preserve these advantages.

  1. Pay attention to coupling. If you need coupling to ensure a close return path, then make sure you understand how this modifies single-ended impedance as discussed above.

  2. Watch for crosstalk when routing. Differential pairs are not immune to crosstalk. A single-ended trace can induce excess crosstalk on one trace in a differential pair. There is also differential crosstalk between two differential pairs. The most effective way to reduce crosstalk is to use larger spacing.

  3. Length tuning structures. Understand how length tuning sections can affect behavior at high frequencies. Length tuning structures will provide skew reduction, but very high bandwidth digital signals can experience slight mode conversion and reflection at high frequencies in length tuning sections.

  4. Minimize via transitions. This is a general rule for differential pairs with high-speed signals and high-frequency interconnects. Vias can create an impedance discontinuity that creates reflection and absorption losses.

  5. Coupling capacitors. Some high-speed interfaces and high-frequency interconnects will use coupling capacitors to block DC offsets along a route. For example, some Ethernet routing protocols and PCIe interfaces use coupling capacitors. The best practice is to place these near the driver.


Differential pair routing

Coupling caps placed near the driver side of a differential interconnect.



These are not the only points to consider in differential pair routing, but this covers a lot of ground. In an upcoming article, we’ll discuss issues involved in analyzing signal integrity on differential pairs, as well as the different types of crosstalk that arise in differential pair interconnects. As I’ll discuss later, and as I have pointed out in discussions on EMI/EMC generally, a primary contributor to failed interconnects is the PCB stackup. Hitting the impedance, noise, and routing goals you need requires success in that area.


Whether you’re designing an ultra-rugged aerospace system or feature-rich IoT products, you’ll need to find a design firm that understands differential pair routing and manufacturing challenges. NWES is an experienced design firm that develops advanced IoT platforms, RF power supply designs, data center products, rugged aerospace systems, and much more. NWES helps aerospace OEMs, defense primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology. We've also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we'll make sure your next rugged electronics system is fully manufacturable at scale. Contact NWES today for a consultation.


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