RISC-V embedded

Overview of RISC-V in Embedded Systems Development

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RISC-V is an instruction set architecture (ISA) based on the principles of reduced instruction set computing. It is published under an open-source license that does not require any fees to be paid in order to use it, unlike the majority of other ISA designs. The standard contains multiple instruction set sizes, including 32-bit and 64-bit variants. RISC-V is a free and open embedded processor specification, so anyone can develop with the standard, although soft cores that can run on FPGAs and microcontrollers are licensed by semiconductor vendors.

The implementation of RISC-V is not enforced at the ISA level, but rather by the digital logic implemented on the end process, either as custom silicon or as a system-on-a-chip (SoC) implementation in an FPGA. This enables designers to create chipsets that are large, small, powerful, or lightweight depending on the needs of the end product. The riscv.org website is a good resource for designers interested in learning more about any available boards, cores, and SoCs. Institutions from around the world are also offering numerous educational programs to help developers learn to use RISC-V.

Overview of RISC-V

All microprocessors use digital logic circuitry that implements an instruction set architecture (ISA), which is the portion of a computer's architecture that assembly-level programmers and compiler designers use to define how data is moved and manipulated in a microprocessor. An ISA defines the commands and instructions that a computer and its microarchitecture can understand natively, as well as their storage, retrieval, and execution.

The RISC-V instruction set architecture (pronounced literally "risk-five") was built using reduced instruction set computing (RISC) principles. Unlike most other ISA designs, it is utilized under an open-source license and no fees are required to build with it [1]. The program began at the University of California, Berkeley, in 2010 with the assistance of unaffiliated volunteers. The foundation of the RISC-V Foundation, which owns, oversees, and publishes the standard. The foundation is located in Switzerland and was renamed RISC-V International only recently.

 

RISC-V ISA

Standard role of an ISA in most microprocessor architectures.

 

RISC-V contains no novel or ground-breaking technological characteristics; the architecture is load-store and is based on well-known RISC concepts. As with other ISAs, the standard provides multiple instruction set tiers. There are 32-bit and 64-bit variants, as well as modifications to floating-point instructions. This enables the production of versions for a vast array of applications, from embedded microcontrollers to desktop computers and supercomputers with vector processors [1].

Licensed vs. Open-Source

The x86 architecture (and related x64 architecture) is utilized in several PCs and laptops across the globe. ARM is utilized by several smartphones and many embedded devices. Both designs are proprietary, and their use requires the payment of a license and fees [2]. Many businesses may be unable to build their own ISA from scratch, and long-term support is a separate issue. Using a licensed core is therefore an attractive option as it eliminates many of the development hurdles involved in implementing an ISA

The RISC-V architecture is a free and open architecture for interprocessors. Its utilization is governed by the BSD Open Source License. This license does not limit the use of ISA for commercial purposes. Implementers of RISC-V are not required to publish the source code for their RISC-V cores. The only requirement of the license is to acknowledge the RISC-V inventors [3].

Using the RISC-V ISA

The RISC-V ISA is designed for usage in a wide variety of applications. The core instruction set consists of 32-bit naturally aligned instructions of fixed length, whereas the ISA permits variable-length extensions in which each instruction can be any number of 16-bit parcels in length, so long as they are naturally aligned. The instruction set standard offers 32-bit and 64-bit address space versions for compatibility with various processor architectures. Although the specification describes a 128-bit flat address space version as an extension of the 32-bit and 64-bit variants, the 128-bit ISA is "not frozen" on purpose due to the lack of actual experience with such large memory systems [4].

Characteristics

RISC-V offers a number of advantages over traditional ISAs, which are decades old and not designed to handle the most recent computing workloads, including openness, simplicity, clean-slate design, modularity, extensibility, and stability. Some advantages include:

  • Permit innovation: Because RISC-V is a layered and versatile ISA, enterprises can design customized processors for cutting-edge applications by implementing the base instruction set and preset and bespoke extensions.

  • Risk reduction: Organizations can reduce risk and investment by utilizing established and common IP building blocks, as well as the growing collection of open tools and development resources available to the development community.

  • Customizability: Due to the fact that implementation is not mandated by the ISA, but rather by the composition of the SoC (System on a chip) and other design parameters, engineers can adjust chipsets to be large, compact, powerful, or lightweight based on the requirements of the devices.

  • Time to market: RISC-V not only reduces development expenses but also aids companies in bringing their goods to market faster through reuse of open-source design data.

Implementation and Products

Technically, RISC-V is platform agnostic and can be used to create a hardware implementation for any type of system, ranging from small embedded microcontrollers to large MPUs and FPGAs. In addition to small embedded systems and personal computers, subsets support supercomputers with vector processors and large-scale 19-inch rack-mounted parallel machines [4].

One of the most useful implementations is on an FPGA as it can be used to build a highly streamlined application processor for advanced applications. These include AI, sensor fusion, 5G, advanced networking equipment, and robotics. Providers of FPGA-compatible soft cores include Andes Technology, Codasip, Bluespec, Cortus, and SiFive. Microsemi, Rumble Development, and VectorBlox. SiFive provides two licenseable core families: the E Series and the U Series.

 

RISC-V FPGA

An FPGA SOM is an excellent platform for implementing a RISC-V-based system.

 

A number of companies are offering or have announced RISC-V-based hardware. These include microcontrollers, SOMs, and SOCs that can run Linux (Yocto), as well as FPGAs that can include multiple RISC-V cores [4]. Among the most notable are:

  • BeagleV, a low-cost, Linux-capable single-board computer
  • HiFive1 microcontroller (Rev B)
  • Seeed Studio Perf-V, which uses a Xilinx Artix-7 RISC-V FPGA
  • SparkFun RED-V RedBoard, a microcontroller that is compatible with Arduino
  • Shakti, a RISC-V chip developed in India by IIT Madras
  • A host of ASICs and application processors, including ASSPs from Renesas and AI/ML ASICs

Due to the fact that RISC-V is a free and open standard, anyone can design and construct their own processors without incurring license fees. Nonetheless, design and engineering costs can run into the millions of dollars, not to mention a lengthier time to market. Therefore, it makes sense to deploy IP cores or processors from third parties [6].

For development, embedded developers can use Yocto and other Linux distributions as these have been ported to run on RISC-V architectures. As of August 2018, more than 80% of the Debian software collection was ported to run on RISC-V. The goal of the Fedora/RISC-V project is to bring Fedora experience to the RV64GC architecture [6]. In addition to these embedded OS options, companies are building developer and debugger tools to be compatible with RISC-V implementations:

  • IAR Systems released the IAR Embedded Workbench for RISC-V, which supports RV32 32-bit RISC-V cores and extensions.
  • Lauterbach's TRACE32 JTAG debuggers now support RISC-V [1].
  • SEGGER has incorporated RISC-V functionality into its J-Link debug probe and Embedded Studio IDE.
  • UltraSOC recommended and facilitated the deployment of a standard trace system [1].

RISC-V vs. ARM

Numerous differences exist between ARM and RISC-V microprocessors. These distinctions impact the applicability of an application in general. While both processor architectures are similar (they are both load-store and RISC), the primary difference between RISC-V and ARM [7] is that RISC-V is open-source while ARM is not. Because of this difference, Designers can freely develop any core architecture that is highly streamlined and application-specific. However, there is little to no support for hardware design or development hurdles when working on a custom design. In contrast, with a licensed RISC-V-based core or ARM implementations, vendors can provide resources to help customers overcome engineering challenges.

Another major difference between RISC-V and ARM is that authorities can ban the export of ARM because it is a proprietary system. ARM-based systems can fall under export control, depending on how RISC-V-based custom silicon or FPGA is used in an end product. Licensed RISC-V cores and implementations can also be export-controlled, but the RISC-V source code cannot. Because RISC-V is an open-source architecture at its core, anybody with an internet connection to review the specification and implement their own design. This is one of the reasons why some Chinese programmers favor RISC-V for future designs [8].

Summarizing Note

If you want to learn more about the RISC-V instruction set architecture (ISA) and the available boards, cores, and system-on-chip (SoC) options for designers, the riscv.org website is a great place to start. The website provides access to debuggers, C compilers, setup and verification tools, SDKs, and other software tools for the RISC-V ecosystem. The source code can be downloaded from the RISC-V repository on GitHub is a valuable resource.

References

  1. J. T. Wednesday, "What is RISC-V and why is it important?," ICS, 12-May-2021. [Link]
  2. "RISC-V," RISC, 24-Jan-2022. [Link]
  3. "History - RISC-V international," RISC, 17-Oct-2020. [Link]
  4. A. Waterman, Y. Lee, D. A. Patterson, and K. Asanovi, "The RISC-V instruction set manual. Volume 1: User-level ISA, version 2.0," 2014. [Link]
  5. S. Matteson, B. Detwiler, T. R. Academy, E. Eckel, and J. Wallen, "RISC-V: What it is, and what benefits it can provide to your organization," TechRepublic, 22-Oct-2020. [Link]
  6. Devopedia. "RISC-V architecture," Devopedia, 15-Feb-2022. [Link]
  7. L. Doyle, "What is the difference between RISC and CISC PDF?," ici2016.org, 03-Nov-2020. [Link]
  8. Electropages, "Arm vs RISC-V: What are the major differences?," Electropages. [Link]

 

NWES is an experienced digital design firm that develops advanced IoT platforms, sensor products, embedded systems, data center products, and much more. NWES helps aerospace OEMs, defense primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology. We've also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we'll make sure your next high speed digital system is fully manufacturable at scale. Contact NWES for a consultation.

 



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