Guide to Sizing and Using Microvias in HDI PCB DesignBy ZM Peterson • Dec 27, 2021
There are two major trends that have driven miniaturization in electronics. Obviously, there is Moore's Law, but this is related to faster speeds and finer manufacturing capabilities. In integrated circuits the two go together, and you can't have one without the other. When we look at the PCB, the situation is quite different.
Miniaturization on the PCB is driven both by miniaturization in semiconductors, as well as the drive towards greater feature density and diversity on the PCB. As a result, PCB manufacturing capabilities have had to catch up so that designers can pack more features onto boards with high yield. HDI PCB design and layout involves building devices with very fine traces and vias in order to make connections between components, and an important structure that enables HDI PCB layout and routing is microvias.
The reliability of HDI PCBs is related to the size of microvia. This is one of the most important HDI design considerations as it enables routing throughout the PCB. The reliability of microvia structures will be a primary determinant of product reliability, so much so that the IPC issued a reliability warning in 2019 specifically related to microvia aspect ratios. In this article, I want to cover some broad design guidelines related to micro via sizing in an HDI PCB in order to ensure new devices remain highly reliable. This is particularly important in devices that require small form factor, high compute, and high component density. Some examples include, edge computing, commercial space and advanced defense electronics.
Microvias in an HDI PCB
Microvias can appear in a PCB in 4 possible arrangements:
- Blind vias: These views span from the surface layer to the very next layer. In thin dielectrics, they could span up to 2 layers as long as the aspect ratio is small enough.
- Buried vias: These views function just like microvias, although they span across internal layers only. Buried vias do not reach a surface layer, they require an attachment to a blind via to reach a surface layer. The same aspect ratio limits on blind vias also apply to buried vias.
- Stacked microvias: These microvias are arrangements where where blind and buried microvias or groups of buried vias are stacked on top of each other. They can span multiple layers as a group.Korea's have reliability concerns that should be considered before they are used in the HDI PCB layout.
- Staggered microvias: Groups of micro views Can also be staggered between multiple layers. It is the standard method for placing microvias vias To route across multiple layers in an HDI stack up And it is viewed as a more reliable method than using stack to microvias.
The graphic below shows the possible arrangement of microvias that are typically used in an HDI PCB stackup. The standard HDI stackup construction method is to use a rigid core (2-4 layers) with a through-hole via that provides access to thin outer dielectric layers (usually up to 3-4 layers).
Example 2 + N + 2 HDI stackup. [Source: NCAB Group]
During fabrication, while the stackup is being built, microvias are placed in each layer sequentially, and the stack up is built up one layer at a time in a sequential lamination process. The challenge for a PCB designer is to choose the stack of the configuration that enables easy routing while also sizing microvias to ensure they are reliable. The reliability concerns arise both during reflow in PCB assembly and later once the device is deployed in the field.
Before the diameter and depth of microvias can be chosen, the PCB stack up needs to be designed. This means that the designer needs to determine the layer count that should be used to support BGA fanout and routing into dense components, particularly fine pitch BGAs. To balance routability and access to fine pitch components microvia sizing only involves two parameters that are selected after the stackup is determined.
- Microvia diameter and pad diameter, the latter of which can be determined from IPC standards based on your product class.
- Micro via depth, which is determined from the layer stack, and particularly from the dielectric thickness that needs to support HDI routing.
In an HDI PCB, the typical way to determine the number of thin outer dielectrics needed in the stack up is to look at the ballout on the largest BGA component on the board. The number of row and column groups can be used to determine a total layer count that will be needed in the HDI stack up. Once the number of layers is determined, it can be compared with the total thickness and you can select a core/dielectric material pair needed to support HDI routing. These thinner dielectrics can support controlled impedance, so they can be used with dense high speed digital devices.
Example non-standard dog bone fanout for a BGA component. [Source: Susy Webb, AltiumLive 2018]
Once the layer thickness is determined, you can set an upper limit on the microvia aspect ratio to ensure reliability. This will also ensure that the pads are not too large so that they will not interfere with routing, yet they will still be large enough to meet annular ring requirements. A typical upper limit on microvia aspect ratio is 2 based on reliability data published in industry literature and from IPC recommendations. I'll discuss more on microvia reliability below.
To ensure a reliable connection to a BGA component, you should select the pad size such that you can fit your pads in between or under solder balls on your finest pitch BGA. For the finest pitch components, this might limit the layer thickness you need to choose in order to sit below a certain aspect ratio for your microvias. By using the finest pitch BGA to size your microvias, you've ensured those microvia sizes will fit under all other BGA's that might have a larger pitch. You could also use larger pad sizes on those coarser BGAs to ensure reliability.
The aspect ratio limit you choose will depend on your fabricator’s capabilities, the end application, and whether you are soldering directly onto a microvia. Microvias should be fabricated such that they are void-free and can survive reflow processes without fracturing at the base or the neck. The microsection image below shows two regions where fracture is common in microvias.
Image showing fracture locations in a microvia due to applied thermal stresses. [Source: Everything You Need to Know About Microvias in Printed Circuit Design]
I always say this when I talk about designing in the HDI regime: the first thing you should do is talk to your fabricator. Different fabricators can place microvias with different aspect ratios very reliably, including in a standard sequential lamination process or high-layer-count HDI process. If they assemble in house, they can at least verify that the board will pass reflow successfully, even at a higher aspect ratio with their process. I've talked to fabricators that will violate the IPC reliability limits as issued in the 2019 warning, i.e., they claim to exceed aspect ratios of 2 without problems. The typical design guideline states that aspect ratios for microvias should be kept below 2, specifically for stacked blind-buried microvias.
It's important to note that this is just a manufacturing reliability, meaning whether the microvias can be reliably fabricated as designed with minimal misregistration as well as whether they can pass through reflow without fracturing due to thermal cycling. Some fabricators might argue that a microvia aspect ratio of 2 is too large, while others will tell you they can reliably fabricate and assemble with higher aspect ratio microvias. What matters is that the microvias and the board will survive once put into service in the field. This requires extensive testing in the lab before deployment. Some examples include modern data center, military, embedded computing, and commercial space applications.
Any PCBA that will be deployed in a harsh environment should undergo extensive controlled environmental testing.
Whether or not the design is reliable in the field is another matter entirely. Highly rugged electronics that carry strict reliability requirements, particularly in areas like automotive and aerospace, might fail even though they were fabricated with high yield and can survive reflow. Just because the devices were fabricated with high yield and were able to pass reflow does not mean they will be highly reliable when the end product is deployed in the field. Further testing is needed, particularly mechanical and thermal shock testing, before a rugged electronics device that uses an HDI PCB can be fully qualified.
How Your PCB Design Services Partner Can Help
Some firms that provide HDI PCB design and layout services will simply try to hit IPC standards while complying with the IPC reliability warning when creating an HDI stack up. This is not a guarantee of reliability in your specific application and use case. It's best for designers to keep this in mind early in the design process and to work closely with test engineering to ensure that the end device will be reliable. If you can get fabrication information from your design house on the front end, then you can rest assured that your design will at least be fabricated and assembled reliably with high yield.
Whether you’re designing an ultra-rugged aerospace system or feature-rich IoT products, you’ll need to find a design firm that understands microvias and HDI manufacturing challenges. NWES is an experienced design firm that develops advanced IoT platforms, RF power supply designs, data center products, aerospace systems, and much more. NWES helps aerospace OEMs, defense primes, and private companies in multiple industries design modern PCBs and create cutting-edge embedded technology. We've also partnered directly with EDA companies and advanced ITAR-compliant PCB manufacturers, and we'll make sure your next high speed digital system is fully manufacturable at scale. Contact NWES for a consultation.